Issued Patents All Time
Showing 51–60 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5781466 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Satoru Tanoi | 1998-07-14 |
| 5739719 | Bias circuit with low sensitivity to threshold variations | Satoru Tanoi | 1998-04-14 |
| 5659258 | Level shifter circuit | Satoru Tanoi, Yasuhiro Tanaka | 1997-08-19 |
| 5652727 | Semiconductor memory device | Yasuhiro Tanaka | 1997-07-29 |
| 5648734 | Buffer circuit and bias circuit | Satoru Tanoi | 1997-07-15 |
| 5596521 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Satoru Tanoi | 1997-01-21 |
| 5577223 | Dynamic random access memory (DRAM) with cache and tag | Satoru Tanoi, Yasuhiro Tanaka | 1996-11-19 |
| 5566115 | Semiconductor memory device | Yasuhiro Tanaka | 1996-10-15 |
| 5511030 | Semiconductor memory device and method of driving same | Yasuhiro Tanaka, Satoru Tanoi | 1996-04-23 |
| 5477496 | Semiconductor memory device having circuits for precharging and equalizing | Yasuhiro Tanaka | 1995-12-19 |