Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10897230 | Bias circuit and amplification apparatus | Tetsuo Endoh | 2021-01-19 |
| 7397309 | Bias circuit for a wideband amplifier driven with low voltage | — | 2008-07-08 |
| 6522563 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2003-02-18 |
| 6510070 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2003-01-21 |
| 6362989 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2002-03-26 |
| 6320778 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2001-11-20 |
| 6249450 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2001-06-19 |
| 6195771 | Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit | Tetsuya Tanabe, Yasuhiro Tokunaga | 2001-02-27 |
| 6104655 | Semiconductor storage device | Atsuhiko Okada | 2000-08-15 |
| 6011709 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 2000-01-04 |
| 5903488 | Semiconductor memory with improved word line structure | — | 1999-05-11 |
| 5875148 | Semiconductor memory | Yasuhiro Tanaka | 1999-02-23 |
| 5821777 | Current amplifier and data bus circuit | — | 1998-10-13 |
| 5781466 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 1998-07-14 |
| 5751177 | Variable level shifter and multiplier suitable for low-voltage differential operation | — | 1998-05-12 |
| 5751665 | Clock distributing circuit | — | 1998-05-12 |
| 5739719 | Bias circuit with low sensitivity to threshold variations | Tetsuya Tanabe | 1998-04-14 |
| 5708621 | Semiconductor memory with improved word line structure | — | 1998-01-13 |
| 5659258 | Level shifter circuit | Tetsuya Tanabe, Yasuhiro Tanaka | 1997-08-19 |
| 5648734 | Buffer circuit and bias circuit | Tetsuya Tanabe | 1997-07-15 |
| 5640117 | Digital signal transmission circuit | — | 1997-06-17 |
| 5596521 | Semiconductor memory with built-in cache | Yasuhiro Tanaka, Tetsuya Tanabe | 1997-01-21 |
| 5592499 | Semiconductor memory device | — | 1997-01-07 |
| 5577223 | Dynamic random access memory (DRAM) with cache and tag | Yasuhiro Tanaka, Tetsuya Tanabe | 1996-11-19 |
| 5559462 | Digital signal transmission circuit | — | 1996-09-24 |