| 8171311 |
Transferring data values via a data bus or storing data values using a selectable representation |
— |
2012-05-01 |
$9,029,000 |
| 7949866 |
Exception types within a secure processing system |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier |
2011-05-24 |
$6,395,000 |
| 7849296 |
Monitoring control for monitoring at least two domains of multi-domain processors |
Luc Orion |
2010-12-07 |
$5,983,000 |
| 7849310 |
Switching between secure and non-secure processing modes |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier |
2010-12-07 |
$5,983,000 |
| 7661104 |
Task following between multiple operating systems |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier +2 more |
2010-02-09 |
$2,142,000 |
| 7661105 |
Exception types within a secure processing system |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier |
2010-02-09 |
$2,142,000 |
| 7549059 |
Transferring data values via a data bus or storing data values using a selectable representation |
— |
2009-06-16 |
$2,450,000 |
| 7487367 |
Apparatus and method for managing access to a memory |
Lionel Belnet, Nicolas Chaussade, Peter Guy Middleton |
2009-02-03 |
$3,794,000 |
| 7448050 |
Handling multiple interrupts in a data processing system utilising multiple operating systems |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier +2 more |
2008-11-04 |
$524,000 |
| 7383587 |
Exception handling control in a secure processing system |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier |
2008-06-03 |
$3,780,000 |
| 7340573 |
Apparatus and method for controlling access to a memory unit |
— |
2008-03-04 |
$1,417,000 |
| 7325083 |
Delivering data processing requests to a suspended operating system |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier +2 more |
2008-01-29 |
$997,000 |
| 7305534 |
Control of access to a memory by a device |
Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton |
2007-12-04 |
$1,449,000 |
| 7305712 |
Security mode switching via an exception vector |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier |
2007-12-04 |
$1,449,000 |
| 7231476 |
Function control for a processor |
Luc Orion, Nicolas Chaussade |
2007-06-12 |
$1,746,000 |
| 7185159 |
Technique for accessing memory in a data processing apparatus |
Lionel Beinet, David Hennah Mansell |
2007-02-27 |
$3,318,000 |
| 7149862 |
Access control in a data processing apparatus |
Andrew David Tune, Peter James Aldworth, Lionel Belnet, David Hennah Mansell |
2006-12-12 |
$1,578,000 |
| 7134003 |
Variable cycle instruction execution in variable or maximum fixed cycle mode to disguise execution path |
— |
2006-11-07 |
$696,000 |
| 7124274 |
Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier +2 more |
2006-10-17 |
$1,509,000 |
| 7117284 |
Vectored interrupt control within a system having a secure domain and a non-secure domain |
Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier +2 more |
2006-10-03 |
$1,540,000 |
| 6272033 |
Status bits for cache memory |
— |
2001-08-07 |
$5,258,000 |
| 5875465 |
Cache control circuit having a pseudo random address generator |
Michael Thomas Kilpatrick, Guy Larri |
1999-02-23 |
$2,152,000 |
| 5802598 |
Data memory access control and method using fixed size memory sections that are sub-divided into a fixed number of variable size sub-sections |
— |
1998-09-01 |
|
| 5675615 |
Apparatus and method for switching asynchronous clock signals |
— |
1997-10-07 |
|
| 5579526 |
Synchronous/asynchronous feedback system having logic circuit for changing the state of the processing core in response to output of synchronous state machine and asynchronous late inputs |
— |
1996-11-26 |
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