Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8429661 | Managing multi-threaded FIFO memory by determining whether issued credit count for dedicated class of threads is less than limit | Marcio T. Oliveira | 2013-04-23 |
| 8201172 | Multi-threaded FIFO memory with speculative read and write capability | Marcio T. Oliveira | 2012-06-12 |
| 8094670 | Method and apparatus for performing network processing functions | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2012-01-10 |
| 8051126 | Method and apparatus for providing an integrated network of processors | Gary D. Hicok | 2011-11-01 |
| 7961178 | Method and system for reordering isochronous hub streams | Patrick R. Marchand | 2011-06-14 |
| 7961733 | Method and apparatus for performing network processing functions | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2011-06-14 |
| 7924868 | Internet protocol (IP) router residing in a processor chipset | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2011-04-12 |
| 7870524 | Method and system for automating unit performance testing in integrated circuit design | Rajeshwaran Selvanesan, Prasad Gharpure, John Douglas Tynefield, Jr. | 2011-01-11 |
| 7756148 | Multi-threaded FIFO memory generator with speculative read and write capability | Marcio T. Oliveira | 2010-07-13 |
| 7685371 | Hierarchical flush barrier mechanism with deadlock avoidance | Samuel H. Duncan, John H. Edmondson, David W. Nuechterlein, Michael A. Woodmansee | 2010-03-23 |
| 7630389 | Multi-thread FIFO memory generator | Marcio T. Oliveira | 2009-12-08 |
| 7631152 | Determining memory flush states for selective heterogeneous memory flushes | Michael A. Woodmansee | 2009-12-08 |
| 7620738 | Method and apparatus for providing an integrated network of processors | Gary D. Hicok | 2009-11-17 |
| 7496788 | Watchdog monitoring for unit status reporting | Robert J. Hasslen, III | 2009-02-24 |
| 7483823 | Building integrated circuits using logical units | — | 2009-01-27 |
| 7437548 | Network level protocol negotiation and operation | — | 2008-10-14 |
| 7397797 | Method and apparatus for performing network processing functions | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2008-07-08 |
| 7383352 | Method and apparatus for providing an integrated network of processors | Gary D. Hicok | 2008-06-03 |
| 7362772 | Network processing pipeline chipset for routing and host packet processing | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2008-04-22 |
| 7363610 | Building integrated circuits using a common database | — | 2008-04-22 |
| 7360213 | Method for promotion and demotion between system calls and fast kernel calls | — | 2008-04-15 |
| 7324547 | Internet protocol (IP) router residing in a processor chipset | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2008-01-29 |
| 7188250 | Method and apparatus for performing network processing functions | Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris | 2007-03-06 |
| 7120653 | Method and apparatus for providing an integrated file system | Radoslav Danilak | 2006-10-10 |
| 6920484 | Method and apparatus for providing an integrated virtual disk subsystem | Radoslav Danilak | 2005-07-19 |