Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159664 | Concurrent memory access operations | Lalit Gupta, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma, El Mehdi Boujamaa | 2024-12-03 |
| 11404096 | Wordline decoder circuitry | Andy Wangkun Chen, Jungtae Kwon | 2022-08-02 |
| 11386937 | System device and method for providing single port memory access in bitcell array by tracking dummy wordline | Lalit Gupta, Bo Zheng, El Mehdi Boujamaa, Fakhruddin Ali Bohra | 2022-07-12 |
| 11222670 | Circuit architecture to derive higher mux from lower mux design | Lalit Gupta, El Mehdi Boujamaa, Bo Zheng, Fakhruddin Ali Bohra, Cyrille Dray +2 more | 2022-01-11 |
| 11004503 | Write assist circuitry | Lalit Gupta, El Mehdi Boujamaa, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma +1 more | 2021-05-11 |
| 10558585 | Dynamic memory scrambling | Yannick Marc Nevers, Bastien Jean Claude Aghetti, Stephane Zonza | 2020-02-11 |
| 9837141 | Read assist circuitry for a memory device | Mikael Brun, Fabrice Blanc | 2017-12-05 |
| 9728249 | Wordline shape enhancer | Cédric Sacha Redeau | 2017-08-08 |
| 9696772 | Controlling access to a memory | Ali Alaoui | 2017-07-04 |
| 9659614 | Integrated keeper circuit | Fabien Leroy | 2017-05-23 |
| 9036427 | Apparatus and a method for erasing data stored in a memory device | Ali Alaoui, Pierre Lemarchand, Bastien Jean Claude Aghetti | 2015-05-19 |
| 8885429 | Memory device and a method for erasing data stored in the memory device | Pierre Lemarchand, Bastien Jean Claude Aghetti, Virgile Javerliac | 2014-11-11 |
| 8742827 | Power gating circuit | Mikael Brun | 2014-06-03 |
| 8493810 | Memory circuitry with write boost and write assist | Gerald Jean Louis Gouya, Hsin-Yu Chen | 2013-07-23 |
| 8355293 | Retention voltage generation | Sebastien Nicolas Ricavy | 2013-01-15 |
| 8305825 | Timing control circuit | Bastien Jean Claude Aghetti | 2012-11-06 |
| 8193847 | Timing circuit and method of generating an output timing signal | Sebastien Nicolas Ricavy, Gerald Jean Louis Gouya | 2012-06-05 |
| 8050114 | Memory device having a single pass-gate transistor per bitline column multiplexer coupled to latch circuitry and method thereof | Bastien Jean Claude Aghetti | 2011-11-01 |
| 8000156 | Memory device with propagation circuitry in each sub-array and method thereof | Christophe Frey | 2011-08-16 |
| 7936578 | Read only memory cell for storing a multiple bit value | Yannick Marc Nevers, Christophe Frey, Mikael Brun | 2011-05-03 |
| 7805645 | Data processing apparatus and method for testing stability of memory cells in a memory device | Christophe Frey | 2010-09-28 |
| 7613052 | Memory device and method of operating such a memory device | Denis Dufourt | 2009-11-03 |
| 7613053 | Memory device and method of operating such a memory device | Sebastien Nicolas Ricavy, Christophe Frey, Denis Dufourt, Vincent Philippe Schuppe | 2009-11-03 |