Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
LK

Lavi Koch — 15 Patents

NVIDIA: 12 patents #582 of 7,811Top 8%
FSFreeescale Semiconductor: 2 patents #1,335 of 3,767Top 40%
Tel Aviv-Yafo, IL: #201 of 1,860 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Lavi Koch has been granted 15 US patents while listed as an inventor at NVIDIA. The first was granted in 2010 and the most recent in December 2025. Lavi Koch ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Lavi Koch in Tel Aviv-Yafo, IL.

Patents per Year

Patents granted per year, 2010 to 2025Bar chart with a peak of 3 patents in 2019.peak 32010: 2 patents20102014: 1 patents20142019: 3 patents20192020: 1 patents20202021: 2 patents20212022: 2 patents20222023: 1 patents20232025: 3 patents2025

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12500830 Link training Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Oded Nadir 2025-12-16
12418393 Power state management for fabrics Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman 2025-09-16
12294522 Mitigating voltage surges in a network device by controlling port bandwidths Michael Weiner 2025-05-06
11637557 Synthesized clock synchronization between network devices Ran Ravid, Aviv Berg, Chen Gaist, Dotan David Levi 2023-04-25
11349780 Enhancing port link-up time Sagi Rotem, Zvi Rechtman, Roee Shapiro 2022-05-31
11283454 Synthesized clock synchronization between network devices Ran Ravid, Aviv Berg, Chen Gaist, Dotan David Levi 2022-03-22
10951545 Network devices Barak Gafni, Zvi Rechtman 2021-03-16
10915154 Raising maximal silicon die temperature using reliability model George Elias, Ido Bourstein, Lior Abramovsky 2021-02-09
10778406 Synthesized clock synchronization between networks devices Chen Gaist, Ran Ravid, Aviv Berg 2020-09-15
10503682 Accessing PCIe configuration data through network Yoni Galezer, Tova Bar Asher 2019-12-10 $7,400,000
10412673 Power-efficient activation of multi-lane ports in a network element Gil Levy, Liron Mula, Aviv Kfir 2019-09-10
10324513 Control of peripheral device data exchange based on CPU power state Idan Burstein, Shlomo Raikin, Noam Bloch 2019-06-18 $44,390,000
8706928 Integrated circuit and method for reducing violations of a timing constraint Roman Mostinski, Leonid Smolyansky 2014-04-22 $6,260,000
7786809 Method of low power PLL for low jitter demanding applications Michael Priel, Sanjay Wadhwa 2010-08-31
7688127 Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilities Michael Priel, Anton Rozen 2010-03-30