| 12418393 |
Power state management for fabrics |
Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman |
2025-09-16 |
| 12294522 |
Mitigating voltage surges in a network device by controlling port bandwidths |
Michael Weiner |
2025-05-06 |
| 11637557 |
Synthesized clock synchronization between network devices |
Ran Ravid, Aviv Berg, Chen Gaist, Dotan David Levi |
2023-04-25 |
| 11349780 |
Enhancing port link-up time |
Sagi Rotem, Zvi Rechtman, Roee Shapiro |
2022-05-31 |
| 11283454 |
Synthesized clock synchronization between network devices |
Ran Ravid, Aviv Berg, Chen Gaist, Dotan David Levi |
2022-03-22 |
| 10951545 |
Network devices |
Barak Gafni, Zvi Rechtman |
2021-03-16 |
| 10915154 |
Raising maximal silicon die temperature using reliability model |
George Elias, Ido Bourstein, Lior Abramovsky |
2021-02-09 |
| 10778406 |
Synthesized clock synchronization between networks devices |
Chen Gaist, Ran Ravid, Aviv Berg |
2020-09-15 |
| 10503682 |
Accessing PCIe configuration data through network |
Yoni Galezer, Tova Bar Asher |
2019-12-10 |
| 10412673 |
Power-efficient activation of multi-lane ports in a network element |
Gil Levy, Liron Mula, Aviv Kfir |
2019-09-10 |
| 10324513 |
Control of peripheral device data exchange based on CPU power state |
Idan Burstein, Shlomo Raikin, Noam Bloch |
2019-06-18 |
| 8706928 |
Integrated circuit and method for reducing violations of a timing constraint |
Roman Mostinski, Leonid Smolyansky |
2014-04-22 |
| 7786809 |
Method of low power PLL for low jitter demanding applications |
Michael Priel, Sanjay Wadhwa |
2010-08-31 |
| 7688127 |
Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilities |
Michael Priel, Anton Rozen |
2010-03-30 |