| 10931266 |
Low power flip-flop element with gated clock |
Ilyas Elkin, Ge Yang, Xi Zhang |
2021-02-23 |
| 10181842 |
Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion |
Ge Yang, Xi Zhang, Lingfei Deng, Hwong-Kwo Lin |
2019-01-15 |
| 9842631 |
Mitigating external influences on long signal lines |
Ge Yang, Hwong-Kwo Lin, Xi Zhang, Haiyan Gong |
2017-12-12 |
| 9110141 |
Flip-flop circuit having a reduced hold time requirement for a scan input |
Hwong-Kwo Lin, Ge Yang, Xi Zhang, Ting-Hsiang Chu |
2015-08-18 |
| 9071240 |
Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains |
Hank Lin, Ge Yang, Xi Zhang, Haiyan Gong |
2015-06-30 |
| 8988123 |
Small area low power data retention flop |
Ge Yang, Hwong-Kwo Lin, Xi Zhang |
2015-03-24 |
| 8866528 |
Dual flip-flop circuit |
Hwong-Kwo Lin, Ge Yang, Xi Zhang, Ting-Hsiang Chu |
2014-10-21 |