Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672461 | Write assist negative bit line voltage generator for SRAM array | Haiyan Gong, Lei Wang, Sing-Rong Li, Pai-Yi Chang | 2020-06-02 |
| 10181842 | Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion | Ge Yang, Xi Zhang, Jiani Yu, Lingfei Deng | 2019-01-15 |
| 9842631 | Mitigating external influences on long signal lines | Ge Yang, Xi Zhang, Jiani Yu, Haiyan Gong | 2017-12-12 |
| 9542992 | SRAM core cell design with write assist | Ge Yang, Fei Song, Xi Zhang, Haiyan Gong | 2017-01-10 |
| 9525401 | Low clocking power flip-flop | Xi Zhang, Ge Yang, Lingfei Deng | 2016-12-20 |
| 9496047 | Memory cell and memory | Jun Yang, Hua Chen, Yong Li, Ju Shen | 2016-11-15 |
| 9484115 | Power savings via selection of SRAM power source | Stephen Felix, Spencer Gold, Jing-Ming Guo, Andreas Gotterba, Jason Golbus +10 more | 2016-11-01 |
| 9390788 | Configurable delay circuit and method of clock buffering | Lei Wang, Spencer Gold, Zhenye Jiang | 2016-07-12 |
| 9355710 | Hybrid approach to write assist for memory array | Haiyan Gong, Lei Wang, Sing-Rong Li, Pai-Yi Chang | 2016-05-31 |
| 9219480 | Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure | Ge Yang, Xi Zhang, Ying-Jui Huang | 2015-12-22 |
| 9183922 | Eight transistor (8T) write assist static random access memory (SRAM) cell | Jun Yang, Ju Shen, Yong Li, Hua Chen | 2015-11-10 |
| 9123438 | Configurable delay circuit and method of clock buffering | Lei Wang, Spencer Gold, Zhenye Jiang | 2015-09-01 |
| 9110141 | Flip-flop circuit having a reduced hold time requirement for a scan input | Ge Yang, Xi Zhang, Jiani Yu, Ting-Hsiang Chu | 2015-08-18 |
| 8988123 | Small area low power data retention flop | Ge Yang, Xi Zhang, Jiani Yu | 2015-03-24 |
| 8866528 | Dual flip-flop circuit | Ge Yang, Xi Zhang, Jiani Yu, Ting-Hsiang Chu | 2014-10-21 |
| 7839170 | Low power single rail input voltage level shifter | Ge Yang, Charles Chew-Yuen Young | 2010-11-23 |
| 7830175 | Low power single-rail-input voltage level shifter | Ge Yang, Charles Chew-Yuen Young | 2010-11-09 |
| 7772885 | Level shifter circuit to shift signals from a logic voltage to an input/output voltage | Ge Yang, Guoqing Ning, Charles Chew-Yuen Young | 2010-08-10 |
| 7772891 | Self-timed dynamic sense amplifier flop circuit apparatus and method | Ge Yang, Guoqing Ning, Beibei Ren, Charles Chew-Yuen Young | 2010-08-10 |
| 7768320 | Process variation tolerant sense amplifier flop design | Ge Yang, Charles Chew-Yuen Young | 2010-08-03 |
| 7649762 | Area efficient high performance memory cell | Ge Yang, Charles Chew-Yuen Young | 2010-01-19 |
| 7643330 | Sequentially-accessed 1R/1W double-pumped single port SRAM with shared decoder architecture | Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young | 2010-01-05 |
| 7626871 | High-speed single-ended memory read circuit | Ge Yang, Charles Chew-Yuen Young | 2009-12-01 |
| 7626854 | 2-write 3-read SRAM design using a 12-T storage cell | Ge Yang, Charles Chew-Yuen Young | 2009-12-01 |
| 7626878 | Active bit line charge keeper | Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young | 2009-12-01 |