Haggai Eran — 13 Patents at NVIDIA

Haggai Eran has been granted 13 US patents while listed as an inventor at NVIDIA. The first was granted in 2012 and the most recent in July 2024. Haggai Eran ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Haggai Eran in Yoqneam Illit, IL.

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Showing 1–13 of 13 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12045178	Devices, methods, and systems for disaggregated memory resources in a computing environment	Dimitrios Syrivelis, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich, James Stephen Fields, Jr. +1 more	2024-07-23
11991073	Dual software interfaces for multiplane devices to separate network management and communication traffic	Inbal Gal, Guy Rozenberg Kunievsky, Jason Gunthorpe, Liran Liss, Vladimir Koushnir	2024-05-21
11757796	Zero-copy processing	Liran Liss, Yuval Shpigelman, Idan Burstein	2023-09-12
11693804	Cross bus memory mapping	Alex Rosenbaum, Oren Duer, Alexander Mikheev, Nitzan Carmi	2023-07-04
11418454	Computational accelerator for packet payload operations	Boris Pismenny, Liran Liss, Ilya Lesokhin, Adi Menachem	2022-08-16
11184439	Communication with accelerator via RDMA-based network adapter	Dotan David Levi, Maxim Fudim, Liran Liss	2021-11-23
11005771	Computational accelerator for packet payload operations	Boris Pismenny, Liran Liss, Ilya Lesokhin, Adi Menachem	2021-05-11
10841243	NIC with programmable pipeline	Dotan David Levi, Liran Liss, Noam Bloch, Idan Burstein, Lior Narkis +1 more	2020-11-17
10218645	Low-latency processing in a network node	Shachar Raindel, Yaniv Saar, Yishai Israel Hadas, Ari Zigler	2019-02-26	$44,463,000
9639464	Application-assisted handling of page faults in I/O operations	Shachar Raindel, Liran Liss, Noam Bloch	2017-05-02	$4,484,000
8914458	Look-ahead handling of page faults in I/O operations	Shachar Raindel, Liran Liss, Noam Bloch	2014-12-16	$9,265,000
8745276	Use of free pages in handling of page faults	Noam Bloch, Shachar Raindel, Liran Liss	2014-06-03	$14,133,000
8234615	Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout	Shyam Ramji, Bella Dubrov, Ari Freund, Edward F. Mark, Timothy A. Schell	2012-07-31	$5,473,000

Haggai Eran — 13 Patents

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