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USPTO Patent Rankings Data through Dec 31, 2025
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Dimitri Argyres — 24 Patents

NMNetlogic Microsystems: 15 patents #12 of 186Top 7%
HP: 7 patents #2,783 of 16,619Top 20%
Broadcom: 2 patents #4,121 of 9,346Top 45%
Corvallis, OR: #133 of 1,763 inventorsTop 8%
Oregon: #1,754 of 28,073 inventorsTop 7%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
Dimitri Argyres has been granted 24 US patents while listed as an inventor at Netlogic Microsystems. The first was granted in 1997 and the most recent in September 2015. Dimitri Argyres ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Dimitri Argyres in Corvallis, OR, US.

Patents per Year

Patents granted per year, 1997 to 2015Bar chart with a peak of 5 patents in 2013.peak 51997: 1 patents19972001: 1 patents2003: 2 patents20032004: 1 patents2005: 2 patents20052006: 1 patents2008: 1 patents20082009: 1 patents2010: 1 patents20102011: 1 patents2013: 5 patents20132014: 5 patents2015: 2 patents2015

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9123417 Content addressable memory with base-three numeral system 2015-09-01 $9,710,000
9019737 Power savings in a content addressable memory device using masked pre-compare operations 2015-04-28 $7,356,000
8837188 Content addressable memory row having virtual ground and charge sharing Ganesh Krishnamurthy 2014-09-16
8773880 Content addressable memory array having virtual ground nodes 2014-07-08
8675798 Systems, circuits, and methods for phase inversion 2014-03-18
8638582 Content addressable memory with base-three numeral system 2014-01-28
8625320 Quaternary content addressable memory cell having one transistor pull-down stack 2014-01-07
8619451 Power savings in a content addressable memory device using masked pre-compare operations 2013-12-31
8582338 Ternary content addressable memory cell having single transistor pull-down stack 2013-11-12
8553441 Ternary content addressable memory cell having two transistor pull-down stack 2013-10-08
8493763 Self-timed match line cascading in a partitioned content addressable memory array 2013-07-23
8462532 Fast quaternary content addressable memory cell 2013-06-11
7868383 Configurable non-volatile logic structure for characterizing an integrated circuit device Bindiganavale S. Nataraj 2011-01-11 $21,980,000
7856524 Transposing of bits in input data to form a comparand within a content addressable memory Varadarajan Srinivasan 2010-12-21 $8,892,000
7589362 Configurable non-volatile logic structure for characterizing an integrated circuit device Bindiganavale S. Nataraj 2009-09-15 $12,387,000
7412561 Transposing of bits in input data to form a comparand within a content addressable memory Varadarajan Srinivasan 2008-08-12 $8,751,000
7050318 Selective match line pre-charging in a CAM device using pre-compare operations 2006-05-23 $7,716,000
6964028 Method of simultaneously displaying schematic and timing data 2005-11-08 $16,653,000
6861876 Pulse evaluate logic-latch 2005-03-01 $8,142,000
6715137 Method of resolving min-time violations in an integrated circuit 2004-03-30 $16,313,000
6591404 Method of automatically finding and fixing min-time violations 2003-07-08 $20,812,000
6564365 Method of simultaneously displaying schematic and timing data 2003-05-13 $16,526,000
6317379 Determine output of a read/write port 2001-11-13 $17,197,000
5644342 Addressing system for an integrated printhead 1997-07-01 $32,947,000