Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9123417 | Content addressable memory with base-three numeral system | — | 2015-09-01 |
| 9019737 | Power savings in a content addressable memory device using masked pre-compare operations | — | 2015-04-28 |
| 8837188 | Content addressable memory row having virtual ground and charge sharing | Ganesh Krishnamurthy | 2014-09-16 |
| 8773880 | Content addressable memory array having virtual ground nodes | — | 2014-07-08 |
| 8675798 | Systems, circuits, and methods for phase inversion | — | 2014-03-18 |
| 8638582 | Content addressable memory with base-three numeral system | — | 2014-01-28 |
| 8625320 | Quaternary content addressable memory cell having one transistor pull-down stack | — | 2014-01-07 |
| 8619451 | Power savings in a content addressable memory device using masked pre-compare operations | — | 2013-12-31 |
| 8582338 | Ternary content addressable memory cell having single transistor pull-down stack | — | 2013-11-12 |
| 8553441 | Ternary content addressable memory cell having two transistor pull-down stack | — | 2013-10-08 |
| 8493763 | Self-timed match line cascading in a partitioned content addressable memory array | — | 2013-07-23 |
| 8462532 | Fast quaternary content addressable memory cell | — | 2013-06-11 |
| 7868383 | Configurable non-volatile logic structure for characterizing an integrated circuit device | Bindiganavale S. Nataraj | 2011-01-11 |
| 7856524 | Transposing of bits in input data to form a comparand within a content addressable memory | Varadarajan Srinivasan | 2010-12-21 |
| 7589362 | Configurable non-volatile logic structure for characterizing an integrated circuit device | Bindiganavale S. Nataraj | 2009-09-15 |
| 7412561 | Transposing of bits in input data to form a comparand within a content addressable memory | Varadarajan Srinivasan | 2008-08-12 |
| 7050318 | Selective match line pre-charging in a CAM device using pre-compare operations | — | 2006-05-23 |
| 6964028 | Method of simultaneously displaying schematic and timing data | — | 2005-11-08 |
| 6861876 | Pulse evaluate logic-latch | — | 2005-03-01 |
| 6715137 | Method of resolving min-time violations in an integrated circuit | — | 2004-03-30 |
| 6591404 | Method of automatically finding and fixing min-time violations | — | 2003-07-08 |
| 6564365 | Method of simultaneously displaying schematic and timing data | — | 2003-05-13 |
| 6317379 | Determine output of a read/write port | — | 2001-11-13 |
| 5644342 | Addressing system for an integrated printhead | — | 1997-07-01 |