Issued Patents All Time
Showing 25 most recent of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417388 | Hardware implementations of activation functions in neural networks | — | 2025-09-16 |
| 11967366 | Reconfigurable compute memory | — | 2024-04-23 |
| 11398273 | Reconfigurable compute memory | — | 2022-07-26 |
| 9349738 | Content addressable memory (CAM) device having substrate array line structure | Varadarajan Srinivasan | 2016-05-24 |
| 8982596 | Content addressable memory having column segment redundancy | Varadarajan Srinivasan, Sandeep Khanna | 2015-03-17 |
| 8913412 | Incremental adaptive match line charging with calibration | Sandeep Khanna, Varadarajan Srinivasan | 2014-12-16 |
| 8767488 | Content addressable memory having half-column redundancy | Varadarajan Srinivasan, Sandeep Khanna | 2014-07-01 |
| 8730704 | Content addressable memory array having local interconnects | John S. Zimmer, Sandeep Khanna, Vinay Iyengar, Chetan Deshpande | 2014-05-20 |
| 8324929 | Integrated circuit with reconfigurable inputs/outputs | Vinay Iyengar, Venkat R. Gaddam | 2012-12-04 |
| 8089794 | Precharge circuits and methods for content addressable memory (CAM) and related devices | Chetan Deshpande | 2012-01-03 |
| 8031501 | Segmented content addressable memory device having pipelined compare operations | Chetan Deshpande, Vinay Iyengar, Sandeep Khanna | 2011-10-04 |
| 7943400 | Integrated circuit device with electronically accessible device identifier | — | 2011-05-17 |
| 7920399 | Low power content addressable memory device having selectable cascaded array segments | Vinay Iyengar, Chetan Deshpande, Sandeep Khanna | 2011-04-05 |
| 7920397 | Memory device having bit line leakage compensation | Sandeep Khanna, Varadarajan Srinivasan | 2011-04-05 |
| 7920398 | Adaptive match line charging | Sandeep Khanna, Chetan Deshpande, Vinay Iyengar | 2011-04-05 |
| 7868383 | Configurable non-volatile logic structure for characterizing an integrated circuit device | Dimitri Argyres | 2011-01-11 |
| 7848129 | Dynamically partitioned CAM array | Chetan Deshpande, Vinay Iyengar | 2010-12-07 |
| 7830691 | Low power content addressable memory | Varadarajan Srinivasan, Sandeep Khanna | 2010-11-09 |
| 7800930 | Precharge circuits and methods for content addressable memory (CAM) and related devices | Chetan Deshpande | 2010-09-21 |
| 7782084 | Integrated circuit with reconfigurable inputs/outputs | Vinay Iyengar, Venkat R. Gaddam | 2010-08-24 |
| 7688609 | Content addressable memory having dynamic match resolution | Varadarajan Srinivasan, Sandeep Khanna | 2010-03-30 |
| 7589362 | Configurable non-volatile logic structure for characterizing an integrated circuit device | Dimitri Argyres | 2009-09-15 |
| 7505295 | Content addressable memory with multi-row write function | Sandeep Khanna | 2009-03-17 |
| 7461295 | Timing failure analysis in a semiconductor device having a pipelined architecture | Vinay Iyengar | 2008-12-02 |
| 7417881 | Low power content addressable memory | Varadarajan Srinivasan, Sandeep Khanna | 2008-08-26 |