Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12217524 | Systems and methods for automated end-to-end text extraction of electronic documents | Keerthan Ramnath, Punitha Chandrasekar, Hui Su, Shyam Subramanian, Rachna Saxena +1 more | 2025-02-04 |
| 11657078 | Automatic identification of document sections to generate a searchable data structure | Ananya Bal, Punitha Chandrasekar, Bidhan Roy | 2023-05-23 |
| 9520194 | Pre-computation based ternary content addressable memory | — | 2016-12-13 |
| 9070435 | Pre-computation based ternary content addressable memory | — | 2015-06-30 |
| 8787059 | Cascaded content addressable memory array having multiple row segment activation | — | 2014-07-22 |
| 8730704 | Content addressable memory array having local interconnects | Bindiganavale S. Nataraj, John S. Zimmer, Sandeep Khanna, Chetan Deshpande | 2014-05-20 |
| 8324929 | Integrated circuit with reconfigurable inputs/outputs | Venkat R. Gaddam, Bindiganavale S. Nataraj | 2012-12-04 |
| 8185689 | Processor with compare operations based on any of multiple compare data segments | Venkat R. Gaddam, Aparna Bharat | 2012-05-22 |
| 8031501 | Segmented content addressable memory device having pipelined compare operations | Bindiganavale S. Nataraj, Chetan Deshpande, Sandeep Khanna | 2011-10-04 |
| 7920399 | Low power content addressable memory device having selectable cascaded array segments | Bindiganavale S. Nataraj, Chetan Deshpande, Sandeep Khanna | 2011-04-05 |
| 7920398 | Adaptive match line charging | Sandeep Khanna, Bindiganavale S. Nataraj, Chetan Deshpande | 2011-04-05 |
| 7848129 | Dynamically partitioned CAM array | Chetan Deshpande, Bindiganavale S. Nataraj | 2010-12-07 |
| 7814267 | Processor with compare operations based on any of multiple compare data segments | Venkat R. Gaddam, Aparna Bharat | 2010-10-12 |
| 7782645 | Selective encoding of data values for memory cell blocks | Venkat R. Gaddam, Rajagopal Krishnaswamy | 2010-08-24 |
| 7782084 | Integrated circuit with reconfigurable inputs/outputs | Venkat R. Gaddam, Bindiganavale S. Nataraj | 2010-08-24 |
| 7461295 | Timing failure analysis in a semiconductor device having a pipelined architecture | Bindiganavale S. Nataraj | 2008-12-02 |