Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6924201 | Heterojunction bipolar transistor and method of producing the same | Masahiro Tanomura, Hidenori Shimawaki, Fumio Harima | 2005-08-02 |
| 6723664 | Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction | Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Shuji Nomura +2 more | 2004-04-20 |
| 6717192 | Schottky gate field effect transistor | — | 2004-04-06 |
| 6483135 | Field effect transistor | Masashi Mizuta, Masaaki Kuzuhara, Yasunobu Nashimoto, Kazunori Asano, Yasunori Mochizuki | 2002-11-19 |
| 6462362 | Heterojunction bipolar transistor having prevention layer between base and emitter | — | 2002-10-08 |
| 6349669 | Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction | Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Shuji Nomura +2 more | 2002-02-26 |
| 6325857 | CVD apparatus | — | 2001-12-04 |
| 6225241 | Catalytic deposition method for a semiconductor surface passivation film | — | 2001-05-01 |
| 6100571 | Fet having non-overlapping field control electrode between gate and drain | Masashi Mizuta, Masaaki Kuzuhara, Yasunobu Nashimoto, Kazunori Asano, Yasunori Mochizuki | 2000-08-08 |
| 6069094 | Method for depositing a thin film | Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Shuji Nomura +2 more | 2000-05-30 |
| 5942792 | Compound semiconductor device having a multilayer silicon structure between an active region and insulator layer for reducing surface state density at interface | — | 1999-08-24 |