| 8402298 |
Array-type processor having delay adjusting circuit for adjusting a clock cycle in accordance with a critical path delay of the data path |
— |
2013-03-19 |
| 8151089 |
Array-type processor having plural processor elements controlled by a state control unit |
Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Toru Awashima +2 more |
2012-04-03 |
| 7752420 |
Configuration layout number controlled adjustable delaying of connection path changes among processors in array to reduce transition glitches |
Yoshitaka Izawa |
2010-07-06 |
| 7523292 |
Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix |
Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Toru Awashima +2 more |
2009-04-21 |
| 6556484 |
Plural line buffer type memory LSI |
Masato Motomura |
2003-04-29 |
| 6490669 |
Memory LSI with compressed data inputting and outputting function |
— |
2002-12-03 |
| 6414880 |
Multiple line buffer type memory LSI |
Masato Motomura |
2002-07-02 |
| 6263413 |
Memory integrated circuit and main memory and graphics memory systems applying the above |
Masato Motomura, Yoshiharu Aimoto |
2001-07-17 |
| 6118718 |
Semiconductor memory device in which a BIT line pair having a high load is electrically separated from a sense amplifier |
— |
2000-09-12 |
| 6034911 |
Semiconductor memory device for a rapid random access |
Yoshiharu Aimoto, Tohru Kimura |
2000-03-07 |
| 5845312 |
System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching |
Tohru Kimura, Yoshiharu Aimoto |
1998-12-01 |
| 5815442 |
Data transfer apparatus with large noise margin and reduced power dissipation |
Yoshiharu Aimoto, Tohru Kimura |
1998-09-29 |
| 5714893 |
Signal transmission circuit |
Yoshiharu Aimoto, Tohru Kimura |
1998-02-03 |