Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11966716 | Apparatus and method for fully parallelized simulated annealing using a self-action parameter | Normann MERTIG, Takashi Takemoto, Shinya Takamaeda, Kasho Yamamoto, Akira Sakai +1 more | 2024-04-23 |
| 11507821 | Neural network circuit and neural network integrated circuit | — | 2022-11-22 |
| 8275973 | Reconfigurable device | Takao Toi, Toru Awashima, Taro Fujii, Toshiro KITAOKA, Koichiro Furuta | 2012-09-25 |
| 8176451 | Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium | Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Taro Fujii +2 more | 2012-05-08 |
| 8151089 | Array-type processor having plural processor elements controlled by a state control unit | Taro Fujii, Koichiro Furuta, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima +2 more | 2012-04-03 |
| 8041925 | Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block | Toshirou Kitaoka, Taro Fujii, Kouichirou Furuta, Toru Awashima, Takao Toi | 2011-10-18 |
| 7793092 | Information processing apparatus and method for using reconfigurable device | Takao Toi, Tooru Awashima, Hirokazu Kami, Takeshi Inuo, Nobuki Kajihara +3 more | 2010-09-07 |
| 7680962 | Stream processor and information processing apparatus | Kenichiro Anjo, Katsumi Togawa, Ryoko Sasaki, Taro Fujii | 2010-03-16 |
| 7650484 | Array—type computer processor with reduced instruction storage | Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami +3 more | 2010-01-19 |
| 7647485 | Data processing system for debugging utilizing halts in a parallel device | Hirokazu Kami, Takao Toi, Toru Awashima, Kenichiro Anjo, Koichiro Furuta +1 more | 2010-01-12 |
| 7523292 | Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix | Taro Fujii, Koichiro Furuta, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima +2 more | 2009-04-21 |
| 7366821 | High-speed memory system | Muneo Fukaishi, Yoshiharu Aimoto, Masakazu Yamashina | 2008-04-29 |
| 7350054 | Processor having array of processing elements whose individual operations and mutual connections are variable | Koichiro Furuta, Taro Fujii | 2008-03-25 |
| 7287146 | Array-type computer processor | Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami +3 more | 2007-10-23 |
| 7120903 | Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus | Takao Toi, Toru Awashima, Yoshiyuki Miyazawa, Noritsugu Nakamura, Taro Fujii +1 more | 2006-10-10 |
| 6738891 | Array type processor with state transition controller identifying switch configuration and processing element instruction address | Taro Fujii, Koichiro Furuta | 2004-05-18 |
| 6639845 | Data holding circuit having backup function | Taro Fujii, Koichiro Furuta | 2003-10-28 |
| 6556484 | Plural line buffer type memory LSI | Yoshikazu Yabe | 2003-04-29 |
| 6505276 | Processing-function-provided packet-type memory system and method for controlling the same | — | 2003-01-07 |
| 6493272 | Data holding circuit having backup function | Taro Fujii, Koichiro Furuta | 2002-12-10 |
| 6424171 | Base cell and two-dimensional array of base cells for programmable logic LSI | Taro Fujii, Koichiro Furuta | 2002-07-23 |
| 6414880 | Multiple line buffer type memory LSI | Yoshikazu Yabe | 2002-07-02 |
| 6356109 | Programmable device | Koichiro Furuta, Taro Fujii | 2002-03-12 |
| 6347055 | Line buffer type semiconductor memory device capable of direct prefetch and restore operations | — | 2002-02-12 |
| 6339341 | Programmable logic LSI | Taro Fujii, Koichiro Furuta | 2002-01-15 |