MN

Masahiko Nakamae

NE Nec: 5 patents #2,830 of 14,502Top 20%
KU Kyushu University, National University: 2 patents #118 of 767Top 20%
SU Sumco: 2 patents #160 of 464Top 35%
NC Nippon Electric Co.: 1 patents #251 of 792Top 35%
SS Sumitomo Mitsubishi Silicon: 1 patents #73 of 146Top 50%
Overall (All Time): #581,032 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
7977221 Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same Masaharu Ninomiya, Koji Matsumoto, Masanobu Miyao 2011-07-12
7767548 Method for manufacturing semiconductor wafer including a strained silicon layer Masaharu Ninomiya, Koji Matsumoto, Masanobu Miyao, Taizoh Sadoh 2010-08-03
7253082 Pasted SOI substrate, process for producing the same and semiconductor device Naoshi Adachi 2007-08-07
6372628 Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor device Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto +5 more 2002-04-16
6091081 Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto +5 more 2000-07-18
5296391 Method of manufacturing a bipolar transistor having thin base region Fumihiko Sato, Mitsuhiro Sugiyama, Tsutomu Tashiro 1994-03-22
4963957 Semiconductor device having bipolar transistor with trench Susumu Ohi, Hiroshi Shiba 1990-10-16
4800177 Semiconductor device having multilayer silicide contact system and process of fabrication thereof 1989-01-24
4191595 Method of manufacturing PN junctions in a semiconductor region to reach an isolation layer without exposing the semiconductor region surface Kunio Aomura, Fujiki Tokuyoshi 1980-03-04