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Home › Nec › Daisuke Ohshima
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Daisuke Ohshima — 8 Patents

Nec: 8 patents #1,746 of 14,502Top 15%
Tokyo, JP: #18,804 of 90,295 inventorsTop 25%
Overall (All Time): #600,572 of 4,157,543Top 15%
8 Patents All Time
Daisuke Ohshima has been granted 8 US patents while listed as an inventor at Nec. The first was granted in 2008 and the most recent in February 2018. Daisuke Ohshima ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list Daisuke Ohshima in Tokyo, JP.

Patents per Year

Patents granted per year, 2008 to 2018Bar chart with a peak of 4 patents in 2014.peak 42008: 1 patents20082013: 2 patents20132014: 4 patents20142018: 1 patents2018

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
9886666 Information processing device, information processing system, information processing method and computer-readable medium Yousuke MOTOHASHI, Hidekazu Sakagami, Shinichiro Kamei 2018-02-06
8810008 Semiconductor element-embedded substrate, and method of manufacturing the substrate Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Katsumi Kikuchi, Yoshiki Nakashima 2014-08-19
8766440 Wiring board with built-in semiconductor element Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima 2014-07-01
8710669 Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer Kentaro Mori, Yoshiki Nakashima, Katsumi Kikuchi, Shintaro Yamamichi 2014-04-29
8692135 Wiring board capable of containing functional element and method for manufacturing same Takuo Funaya, Shintaro Yamamichi, Yoshiki Nakashima 2014-04-08
8569892 Semiconductor device and manufacturing method thereof Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Katsumi Kikuchi +1 more 2013-10-29
8450843 Semiconductor device and method for designing the same Hideki Sasaki, Takuo Funaya 2013-05-28
7434190 Analysis method and analysis apparatus of designing transmission lines of an integrated circuit packaging board Hirobumi Inoue, Jun Sakai, Mitsuru Furuya 2008-10-07

Frequent Collaborators

Yoshiki Nakashima5 shared
Shintaro Yamamichi5 shared
Kentaro Mori4 shared
Katsumi Kikuchi4 shared
Hideya Murai3 shared
Takuo Funaya2 shared

Nearby-Ranked Inventors

Suryatej Gundavelli8
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Yang Ji8
Koichi Sekimizu8
Sandeep Rekhi8
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Jonatan Hörder8