Issued Patents All Time
Showing 126–149 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822294 | High holding voltage LVTSCR | Ann Concannon, Peter J. Hopper | 2004-11-23 |
| 6815732 | High-voltage silicon controlled rectifier structure | Hon Kin Chiu | 2004-11-09 |
| 6798641 | Low cost, high density diffusion diode-capacitor | Peter J. Hopper, Philipp Lindorfer, Andrew Strachan | 2004-09-28 |
| 6797555 | Direct implantation of fluorine into the channel region of a PMOS device | Peter J. Hopper, Prasad Chaparala, Philipp Lindorfer | 2004-09-28 |
| 6784029 | Bi-directional ESD protection structure for BiCMOS technology | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2004-08-31 |
| 6777784 | Bipolar transistor-based electrostatic discharge (ESD) protection structure with a heat sink | Peter J. Hopper | 2004-08-17 |
| 6720624 | LVTSCR-like structure with internal emitter injection control | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2004-04-13 |
| 6717219 | High holding voltage ESD protection structure for BiCMOS technology | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2004-04-06 |
| 6707117 | Method of providing semiconductor interconnects using silicide exclusion | Peter J. Hopper, Philipp Lindorfer, Andy Strachon, Peter Johnson | 2004-03-16 |
| 6690069 | Low voltage complement ESD protection structures | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2004-02-10 |
| 6667867 | Stable BJT electrostatic discharge protection clamp | Peter J. Hopper | 2003-12-23 |
| 6660602 | Stand-alone triggering structure for ESD protection of high voltage CMOS | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2003-12-09 |
| 6653716 | Varactor and method of forming a varactor with an increased linear tuning range | Pascale Francis, Peter J. Hopper | 2003-11-25 |
| 6639784 | Wedge-shaped high density capacitor and method of making the capacitor | Peter J. Hopper, Philipp Lindorfer, Kyuwoon Hwang, Andy Strachan | 2003-10-28 |
| 6586317 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage | Andy Strachan, Peter J. Hopper | 2003-07-01 |
| 6560081 | Electrostatic discharge (ESD) protection circuit | Peter J. Hopper | 2003-05-06 |
| 6559507 | Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking | Andy Strachan | 2003-05-06 |
| 6548868 | ESD protection clamp with internal zener diode | David Tsuei | 2003-04-15 |
| 6541801 | Triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes | Peter J. Hopper | 2003-04-01 |
| 6498373 | ESD protection CMOS structure with dynamic substrate control | Peter J. Hopper | 2002-12-24 |
| 6492859 | Adjustable electrostatic discharge protection clamp | Peter J. Hopper | 2002-12-10 |
| 6433368 | LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node | Peter J. Hopper | 2002-08-13 |
| 6407445 | MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink | Peter J. Hopper | 2002-06-18 |
| 6355959 | Gate electrode controllable electrostatic discharge (ESD) protection structure having a MOSFET with source and drain regions in separate wells | Peter J. Hopper, Manuel Carneiro | 2002-03-12 |