RM

Ranjan J. Mathew

NS National Semiconductor: 30 patents #28 of 2,238Top 2%
IN Intel: 3 patents #10,349 of 30,777Top 35%
📍 San Jose, CA: #1,784 of 32,062 inventorsTop 6%
🗺 California: #15,031 of 386,348 inventorsTop 4%
Overall (All Time): #108,761 of 4,157,543Top 3%
33
Patents All Time

Issued Patents All Time

Showing 26–33 of 33 patents

Patent #TitleCo-InventorsDate
5328079 Method of and arrangement for bond wire connecting together certain integrated circuit components Arnold R. Smith, Luu Thanh Nguyen 1994-07-12
5270262 O-ring package Andrew Switky, Chok J. Chia 1993-12-14
5208186 Process for reflow bonding of bumps in IC devices 1993-05-04
4963233 Glass conditioning for ceramic package plating 1990-10-16
4922322 Bump structure for reflow bonding of IC devices 1990-05-01
4800178 Method of electroplating a copper lead frame with copper Billy J. Lang, II 1989-01-24
4714517 Copper cleaning and passivating for tape automated bonding Devi P. Malladi, Divyesh P. Shah 1987-12-22
4589962 Solder plating process and semiconductor product Vijay M. Sajja, Jagdish Belane 1986-05-20