Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11776621 | Memory device for increasing write margin during write operation and reducing current leakage during standby operation and operation method thereof | Chien-Tung Liu, CHIH-JUNG LIU | 2023-10-03 |
| 11741968 | Personalized voice conversion system | Tay-Jyi Lin, Yu Chia Hu, Yi-Hsuan Ting, Ching-Wei Yeh | 2023-08-29 |
| 11404112 | Low-voltage low-power memory device with read, write, hold, and standby assist voltages and operation method thereof | Chien-Tung Liu, Hao Wang | 2022-08-02 |
| 11309016 | Variable-latency device to reduce sense error in multi-level multi-bit sensing scheme | Tay-Jyi Lin, Yu Chia Hu, Yi-Hsuan Ting | 2022-04-19 |
| 10971196 | Single-ended sense amplifier | Chien-Tung Liu | 2021-04-06 |
| 10812057 | Time detection circuit and time detection method | Pei-Yuan Chou, Chuen-Shiu Chen | 2020-10-20 |
| 10726928 | Computation speed compensation circuit and compensation method thereof | Tay-Jyi Lin, Ting-Yu Shyu, Chiao-Chuan Huang | 2020-07-28 |
| 10282209 | Speculative lookahead processing device and method | Tay-Jyi Lin, Ting-Yu Shyu, Yi-Hsuan Ting | 2019-05-07 |
| 10127976 | Static random access memory cell array, static random access memory cell and operating method thereof | Yung-Chen Chien | 2018-11-13 |
| 10009017 | On-chip apparatus and method for jitter measurement | Pei-Yuan Chou, Yeong-Jar Chang | 2018-06-26 |
| 9755620 | Device for detecting and correcting timing error and method for designing typical-case timing using the same | Tay-Jyi Lin, Hong LIN, Ting-Yu Shyu | 2017-09-05 |
| 8933726 | Dynamic voltage scaling system having time borrowing and local boosting capability | — | 2015-01-13 |
| 8824185 | NOR-type ROM with hierarchical-BL structure, dynamic segmentation shielding, and source programming | Chao-Hsiang Wang | 2014-09-02 |
| 8743592 | Memory circuit properly workable under low working voltage | Pei Yao Chang | 2014-06-03 |
| 8650520 | Integrated circuit module and manufacturing methods and application thereof | Shu Yi Yang, Chen-Hsien Hsu | 2014-02-11 |
| 8294498 | Clock de-skewing delay locked loop circuit | Chun-Yuan Cheng, Chih-Chiang Liu | 2012-10-23 |
| 8111756 | Method for reducing computational complexity of video compression standard | Jiun-In Guo, Jia-Wei Chen, Chun-Hao Chang, Yi-Huan Ou Yang, Chien-Chang Lin | 2012-02-07 |
| 8090019 | Intra prediction circuit device applied to the H.264 video coding standard | Jiun-In Guo, Jia-Wei Chen | 2012-01-03 |
| 8000120 | Read and match circuit for low-voltage content addressable memory | Tai-An Chen | 2011-08-16 |
| 7865025 | Data processing method in embedded block coding with optimized truncation module | Ying Xu, Ching-Wei Yeh | 2011-01-04 |
| 7756236 | Phase detector | Yi Wang | 2010-07-13 |
| 7738713 | Method for processing digital image with discrete wavelet transform and apparatus for the same | Zhi-Xin Lin, Ching-Wei Yeh | 2010-06-15 |
| 7724975 | Design techniques and their circuit designs for versatile and scalable video coding | Jiun-In Guo, Kuan-Hung Chen | 2010-05-25 |
| 7667993 | Dual-ported and-type match-line circuit for content-addressable memories | Chao Wang, Chieh-Jen Cheng, Tien-Fu Chen | 2010-02-23 |
| 7663938 | Tree-style AND-type match circuit device applied to content addressable memory | — | 2010-02-16 |