Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12260321 | Data feature augmentation system and method for low-precision neural network | Fu-Cheng Tsai, Yi-Ching Kuo, Chih-Sheng Lin, Shyh-Shyuan Sheu, Shih-Chieh Chang | 2025-03-25 |
| 11741968 | Personalized voice conversion system | Yu Chia Hu, Yi-Hsuan Ting, Ching-Wei Yeh, Jinn-Shyan Wang | 2023-08-29 |
| 11699428 | Method for converting vibration to voice frequency wirelessly | Chun-Ming Huang | 2023-07-11 |
| 11567731 | Device for computing an inner product | — | 2023-01-31 |
| 11514889 | Device and method for clarifying dysarthria voices | Che Chia Pai, Hsi Che Wang, Ching-Wei Yeh | 2022-11-29 |
| 11500964 | Device for computing the inner product of vectors | — | 2022-11-15 |
| 11363386 | System for converting vibration to voice frequency wirelessly | Chun-Ming Huang | 2022-06-14 |
| 11328709 | System for improving dysarthria speech intelligibility and method thereof | Ching-Hau Sung, Che Chia Pai, Ching-Wei Yeh | 2022-05-10 |
| 11309016 | Variable-latency device to reduce sense error in multi-level multi-bit sensing scheme | Yu Chia Hu, Yi-Hsuan Ting, Jinn-Shyan Wang | 2022-04-19 |
| 11222650 | Device and method for generating synchronous corpus | Ching-Wei Yeh, Shun Pu Yang, Chen Zong Liao | 2022-01-11 |
| 10726928 | Computation speed compensation circuit and compensation method thereof | Ting-Yu Shyu, Chiao-Chuan Huang, Jinn-Shyan Wang | 2020-07-28 |
| 10282209 | Speculative lookahead processing device and method | Jinn-Shyan Wang, Ting-Yu Shyu, Yi-Hsuan Ting | 2019-05-07 |
| 9755620 | Device for detecting and correcting timing error and method for designing typical-case timing using the same | Jinn-Shyan Wang, Hong LIN, Ting-Yu Shyu | 2017-09-05 |
| 9064153 | Video device for realtime pedaling frequency estimation | Ching-Wei Yeh, Yuan-Hsiang Miao, Shau-Chian Tang | 2015-06-23 |
| 8589718 | Performance scaling device, processor having the same, and performance scaling method thereof | Chi-Hung Lin, Pi-Cheng Hsiao, Gin-Kou Ma | 2013-11-19 |
| 8499188 | Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal | Chou-Kun Lin, Pi-Cheng Hsiao, Yuan-Hua Chu | 2013-07-30 |
| 7877741 | Method and corresponding apparatus for compiling high-level languages into specific processor architectures | Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen, I-Tao Liao, Po-Han Huang | 2011-01-25 |
| 7406588 | Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer | Chein-Wei Jen, Chih-Wei Liu, Po-Han Huang, Wei-Sheng Huang, Chan-Hao Chang | 2008-07-29 |
| 7404048 | Inter-cluster communication module using the memory access network | Pi-Chen Hsiao, Chih-Wei Liu, Chein-Wei Jen, I-Tao Liao, Po-Han Huang | 2008-07-22 |