Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12107002 | Manufacturing method of semiconductor structure | Chuan-Lin HSIAO | 2024-10-01 |
| 11935780 | Semiconductor structure and manufacturing method thereof | Chuan-Lin HSIAO | 2024-03-19 |
| 11659707 | Method of manufacturing a semiconductor structure | Ching-Chia Huang | 2023-05-23 |
| 11582844 | Detection circuit for detecting light-off modes performed by silicon-controlled dimmer | Yue Zheng, Xiao-Bo Hu | 2023-02-14 |
| 11570861 | Light-emitting diode (LED) drive power supply and controller thereof | Yue Zheng, Xiao-Bo Hu | 2023-01-31 |
| 11488964 | Method of manufacturing semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region | Ching-Chia Huang | 2022-11-01 |
| 11482419 | Method for preparing transistor device | Jhen-Yu Tsai, Tseng-Fu Lu | 2022-10-25 |
| 11315930 | Semiconductor structure and method of manufacturing the same | Ching-Chia Huang | 2022-04-26 |
| 11101273 | Semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region | Ching-Chia Huang | 2021-08-24 |
| 10937886 | Semiconductor device with negative capacitance material in buried channel | Ching-Chia Huang, Tseng-Fu Lu | 2021-03-02 |
| 10903080 | Transistor device and method for preparing the same | Jhen-Yu Tsai, Tseng-Fu Lu | 2021-01-26 |
| 10825931 | Semiconductor device with undercutted-gate and method of fabricating the same | Ching-Chia Huang, Tseng-Fu Lu | 2020-11-03 |
| 10825898 | Semiconductor layout structure including asymmetrical channel region | Jhen-Yu Tsai, Tseng-Fu Lu | 2020-11-03 |
| 10818800 | Semiconductor structure and method for preparing the same | Cheng-Hsien Hsieh, Tseng-Fu Lu, Jhen-Yu Tsai, Ching-Chia Huang | 2020-10-27 |
| 10763212 | Semiconductor structure | Cheng-Hsien Hsieh, Ching-Chia Huang, Chen-Lun Ting, Tseng-Fu Lu | 2020-09-01 |
| 10559661 | Transistor device and semiconductor layout structure including asymmetrical channel region | Jhen-Yu Tsai, Tseng-Fu Lu | 2020-02-11 |
| 10559560 | Semiconductor electrostatic discharge protection device | Fang-Wen Liu, Tseng-Fu Lu | 2020-02-11 |
| 10461191 | Semiconductor device with undercutted-gate and method of fabricating the same | Ching-Chia Huang, Tseng-Fu Lu | 2019-10-29 |
| 10446556 | Method for preparing a semiconductor memory structure | — | 2019-10-15 |
| 10381351 | Transistor structure and semiconductor layout structure | Ching-Chia Huang, Tseng-Fu Lu | 2019-08-13 |
| 10242978 | Semiconductor electrostatic discharge protection device | Fang-Wen Liu, Tseng-Fu Lu | 2019-03-26 |
| 9985105 | Method of manufacturing a PMOS transistor comprising a dual work function metal gate | Shin-Yu Nieh, Tieh-Chiang Wu, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee | 2018-05-29 |
| 9401363 | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices | Kuo-Chen Wang, Sriraj Manavalan | 2016-07-26 |
| 9368494 | Semiconductor device and method of manufacturing the same | — | 2016-06-14 |
| 9343547 | Method for fabricating a recessed channel access transistor device | Tieh-Chiang Wu | 2016-05-17 |