Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7086027 | Method and apparatus for constraint graph based layout compaction for integrated circuits | Alexander Marchenko, Mikhail Sotnikov | 2006-08-01 |
| 6434721 | Method and apparatus for constraint graph based layout compaction for integrated circuits | Alexander Marchenko, Mikhail Sotnikov | 2002-08-13 |
| 6075934 | Method for optimizing contact pin placement in an integrated circuit | Mohankumar Guruswamy, Srilata Raman, Robert L. Maziasz | 2000-06-13 |
| 5984510 | Automatic synthesis of standard cell layouts | Mohan Guruswamy, Daniel Dulitz, Robert L. Maziasz, Srilata Raman, Andrea Berens | 1999-11-16 |
| 5987086 | Automatic layout standard cell routing | Srilata Raman, Mohankumar Guruswamy, Daniel Dulitz, Robert L. Maziasz | 1999-11-16 |