PL

Ping-Wei Lin

MV Mosel Vitelic: 7 patents #35 of 482Top 8%
SS Silicon Integrated Systems: 1 patents #128 of 259Top 50%
UM United Microelectronics: 1 patents #2,686 of 4,560Top 60%
Overall (All Time): #519,713 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDate
7651909 Method for fabricating metal-insulator-metal capacitor Chin-Chia Wu, Chao-Sheng Chiang 2010-01-26
6864150 Manufacturing method of shallow trench isolation Gwo-Chyuan Kuoh, Chao-Sheng Chiang 2005-03-08
6551900 Trench gate oxide formation method Yifu Chung, Leon Chang 2003-04-22
6355974 Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator Ming-Kuan Kao, Jui-Ping Li 2002-03-12
6261930 Method for forming a hemispherical-grain polysilicon Jui-Ping Li, Ming-Kuan Kao, Yi-Shin Chang 2001-07-17
6261966 Method for improving trench isolation Jui-Ping Li, Ming-Kuan Kao, Hui-ching Lin 2001-07-17
6191003 Method for planarizing a polycrystalline silicon layer deposited on a trench Chien-Hung Chen, Jui-Ping Li, Yen-Jung Chang 2001-02-20
6171904 Method for forming rugged polysilicon capacitor Jui-Ping Li, Ming-Kuan Kao 2001-01-09
6071794 Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator Ming-Kuan Kao, Jui-Ping Li 2000-06-06
6066529 Method for enlarging surface area of a plurality of hemi-spherical grains on the surface of a semiconductor chip Jui-Ping Li, Ming-Kuan Kao, Yi-Fu Chung 2000-05-23