Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6355524 | Nonvolatile memory structures and fabrication methods | Hsing Tuan, Chung Wai Leung, Thomas Chang | 2002-03-12 |
| 6191997 | Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. | Jin Seung Son | 2001-02-20 |
| 6172554 | Power supply insensitive substrate bias voltage detector circuit | Pochung Young | 2001-01-09 |
| 6133597 | Biasing an integrated circuit well with a transistor electrode | Huoy-Jong Wu, Chung-Cheng Wu, Saysamone Pittikoun, Wen-Wei Lo | 2000-10-17 |
| 6011737 | DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle | Lawrence Liu, Michael A. Murray | 2000-01-04 |
| 5986474 | Data line bias circuit | Jinyong Chung, Pochung Young | 1999-11-16 |
| 5966338 | Dram with new I/O data path configuration | Lawrence Liu, Michael A. Murray | 1999-10-12 |
| 5949722 | I/O bias circuit insensitive to inadvertent power supply variations for MOS memory | Lawrence Liu, Michael A. Murray | 1999-09-07 |
| 5912571 | Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up | Lawrence Liu, Michael A. Murray | 1999-06-15 |
| 5907257 | Generation of signals from other signals that take time to develop on power-up | Lawrence Liu, Michael A. Murray | 1999-05-25 |
| 5889414 | Programmable circuits | Lynne Watters, Sharlin Fang | 1999-03-30 |
| 5844296 | Space saving laser programmable fuse layout | Michael A. Murray, Lawrence Liu | 1998-12-01 |
| 5838622 | Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs | Lawrence Liu, Michael A. Murray | 1998-11-17 |
| 5838072 | Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes | Lawrence Liu, Michael A. Murray | 1998-11-17 |
| 5828609 | Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking | Lawrence Liu, Michael A. Murray | 1998-10-27 |
| 5812474 | I/O bias circuit insensitive to inadvertent power supply variations for MOS memory | Lawrence Liu, Michael A. Murray | 1998-09-22 |
| 5781488 | DRAM with new I/O data path configuration | Lawrence Liu, Michael A. Murray | 1998-07-14 |
| 5767737 | Methods and apparatus for charging a sense amplifier | Lawrence Liu, Michael A. Murray | 1998-06-16 |
| 5768200 | Charging a sense amplifier | Lawrence Liu, Michael A. Murray | 1998-06-16 |
| 5761112 | Charge storage for sensing operations in a DRAM | Michael A. Murray, Lawrence Liu | 1998-06-02 |
| 5757710 | DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle | Lawrence Liu, Michael A. Murray | 1998-05-26 |
| 5440246 | Programmable circuit with fusible latch | Michael A. Murray, Hsing Tuan | 1995-08-08 |
| 5245583 | Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method | Hsing Tuan, Lynne Hannah | 1993-09-14 |