Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11438315 | Methods, systems, apparatuses, and devices for providing durable forward confidentiality during communications between devices | — | 2022-09-06 |
| 10797879 | Methods and systems to facilitate authentication of a user | — | 2020-10-06 |
| 10742042 | Dual system hybrid charger management | Jace W. Files, Gerald R. Pelissier | 2020-08-11 |
| 10313881 | System and method of authentication by leveraging mobile devices for expediting user login and registration processes online | — | 2019-06-04 |
| 7244653 | Method and structure in the manufacture of mask read only memory | Yuan-Hua Kao | 2007-07-17 |
| 6011737 | DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle | Li-Chun Li, Michael A. Murray | 2000-01-04 |
| 5966338 | Dram with new I/O data path configuration | Michael A. Murray, Li-Chun Li | 1999-10-12 |
| 5949722 | I/O bias circuit insensitive to inadvertent power supply variations for MOS memory | Li-Chun Li, Michael A. Murray | 1999-09-07 |
| 5912571 | Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up | Li-Chun Li, Michael A. Murray | 1999-06-15 |
| 5907257 | Generation of signals from other signals that take time to develop on power-up | Michael A. Murray, Li-Chun Li | 1999-05-25 |
| 5844296 | Space saving laser programmable fuse layout | Michael A. Murray, Li-Chun Li | 1998-12-01 |
| 5838072 | Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes | Li-Chun Li, Michael A. Murray | 1998-11-17 |
| 5838622 | Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs | Li-Chun Li, Michael A. Murray | 1998-11-17 |
| 5828609 | Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking | Li-Chun Li, Michael A. Murray | 1998-10-27 |
| 5812474 | I/O bias circuit insensitive to inadvertent power supply variations for MOS memory | Li-Chun Li, Michael A. Murray | 1998-09-22 |
| 5781488 | DRAM with new I/O data path configuration | Michael A. Murray, Li-Chun Li | 1998-07-14 |
| 5768200 | Charging a sense amplifier | Michael A. Murray, Li-Chun Li | 1998-06-16 |
| 5767737 | Methods and apparatus for charging a sense amplifier | Michael A. Murray, Li-Chun Li | 1998-06-16 |
| 5761112 | Charge storage for sensing operations in a DRAM | Michael A. Murray, Li-Chun Li | 1998-06-02 |
| 5757710 | DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle | Li-Chun Li, Michael A. Murray | 1998-05-26 |