Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6965853 | Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elements | Hiroyuki Kuzuma | 2005-11-15 |
| 6427225 | Method and apparatus for verification of a circuit layout | Osamu Kitada, Hironobu Taoka | 2002-07-30 |
| 5699264 | Semiconductor circuit design verifying apparatus | Yoshiki Nakamura, Hirofumi Yamamoto | 1997-12-16 |