Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6484303 | Apparatus for layout designing of semiconductor device, method of layout designing, and semiconductor device | — | 2002-11-19 |
| 6427225 | Method and apparatus for verification of a circuit layout | Terutoshi Yamasaki, Hironobu Taoka | 2002-07-30 |