Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6411563 | Semiconductor integrated circuit device provided with a logic circuit and a memory circuit and being capable of efficient interface between the same | Toshiaki Kawasaki | 2002-06-25 |
| 6411560 | Semiconductor memory device capable of reducing leakage current flowing into substrate | Hiroaki Tanizaki, Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato +3 more | 2002-06-25 |
| 6384674 | Semiconductor device having hierarchical power supply line structure improved in operating speed | Hiroaki Tanizaki, Tsukasa Ooishi, Shigeki Tomishima, Masatoshi Ishikawa, Hideto Hidaka | 2002-05-07 |
| 6373315 | Signal potential conversion circuit | Shigeki Tomishima, Tsukasa Ooishi | 2002-04-16 |
| 6118710 | Semiconductor memory device including disturb refresh test circuit | — | 2000-09-12 |
| 6058053 | Semiconductor memory device capable of high speed operation and including redundant cells | Tsukasa Ooishi, Hiroshi Kato, Shigeki Tomishima, Hiroki Shimano | 2000-05-02 |
| 6031781 | Semiconductor memory device allowing high-speed activation of internal circuit | Shigeki Tomishima, Tsukasa Ooishi, Masatoshi Ishikawa | 2000-02-29 |
| 6005294 | Method of arranging alignment marks | Mikio Asakura, Kyoji Yamasaki | 1999-12-21 |
| 5917766 | Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably | Mikio Asakura, Tadaaki Yamauchi, Koji Tanaka | 1999-06-29 |
| 5812492 | Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal | Tadaaki Yamauchi, Mikio Asakura | 1998-09-22 |
| 5744998 | Internal voltage detecting circuit having superior responsibility | Takashi Ito, Tadaaki Yamauchi | 1998-04-28 |
| 5716889 | Method of arranging alignment marks | Mikio Asakura, Kyoji Yamasaki | 1998-02-10 |