Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159605 | Unevenness correction data generation device | Takashi Sakamoto, Hiroshi Murase, Mitsuo Hagiwara, Hideaki Suzuki, Kazunori Yoshizawa | 2024-12-03 |
| 12148402 | Panel drive circuit | Takashi Sakamoto, Mitsuo Hagiwara, Norimasa Senda, Yoshihide Minegishi, Hiroshi Murase | 2024-11-19 |
| 11990104 | Input signal correction device | Takashi Sakamoto, Yoshihide Minegishi, Ryohei Hatta, Norimasa Senda | 2024-05-21 |
| 11823610 | Input signal correction device | Takashi Sakamoto, Yoshihide Minegishi, Ryohei Hatta, Norimasa Senda | 2023-11-21 |
| 10750148 | Unevenness correction system, unevenness correction apparatus and panel drive circuit | Takashi Sakamoto, Keisuke Okada | 2020-08-18 |
| 7984223 | Information device including main processing circuit, interface circuit, and microcomputer | Hideo Nagano, Kikuo Muramatsu, Masayuki Koyama, Tomoko Ando, Motoki Higashida +1 more | 2011-07-19 |
| 7716410 | Information device including main processing circuit, interface circuit, and microcomputer | Hideo Nagano, Kikuo Muramatsu, Masayuki Koyama, Tomoko Ando, Motoki Higashida +1 more | 2010-05-11 |
| 7237175 | Memory circuit | Koji Nii, Atsuo Mangyo, Takeshi Fujino | 2007-06-26 |
| RE39579 | Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system | Akira Yamazaki, Shigeki Tomishima, Tadato Yamagata | 2007-04-17 |
| 6756803 | Semiconductor device downsizing its built-in driver | Manabu Miura, Takekazu Yamashita | 2004-06-29 |
| 6724237 | Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity | Takekazu Yamashita, Manabu Miura | 2004-04-20 |
| 6715117 | Method of testing a semiconductor memory device | Atsuo Mangyo, Manabu Miura | 2004-03-30 |
| 6570572 | Line delay generator using one-port RAM | Manabu Miura, Mikio Tada | 2003-05-27 |
| 6512707 | Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method | Manabu Miura | 2003-01-28 |
| 6310815 | Multi-bank semiconductor memory device suitable for integration with logic | Tadato Yamagata, Akira Yamazaki, Shigeki Tomishima, Yoshio Yukinari, Atsushi Miyanishi | 2001-10-30 |
| 6163493 | Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit | Tadato Yamagata, Shigeki Tomishima, Akira Yamazaki | 2000-12-19 |
| 6092227 | Test circuit | Hideki Toki, Akira Kitaguchi, Kiyoyuki Shiroshima, Masaaki Matsuo, Tsuyoshi Saitoh | 2000-07-18 |
| 6043522 | Field effect transistor array including doped two-cell isolation region for preventing latchup | Michio Nakajima, Akira Kitaguchi, Kiyoyuki Shiroshima, Takekazu Yamashita, Masaaki Matsuo | 2000-03-28 |
| 6040614 | Semiconductor integrated circuit including a capacitor and a fuse element | Akira Kitaguchi, Michio Nakajima, Kaoru Motonami, Kiyoyuki Shiroshima, Takekazu Yamashita | 2000-03-21 |
| 6025733 | Semiconductor memory device | Tuyoshi Saitoh, Akira Kitaguchi, Masaaki Matsuo, Toshio Nakano, Yuko Sudo | 2000-02-15 |
| 5973953 | Semiconductor memory device having improved bit line structure | Takekazu Yamashita, Kiyoyuki Shiroshima, Michio Nakajima, Hideki Toki, Tuyoshi Saitoh | 1999-10-26 |
| 5949268 | Variable delay circuit for varying delay time and pulse width | Manabu Miura | 1999-09-07 |
| 5930194 | Semiconductor memory device capable of block writing in large bus width | Tadato Yamagata, Akira Yamazaki, Shigeki Tomishima, Masashi Matsumura | 1999-07-27 |
| 5910181 | Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core | Akira Yamazaki, Shigeki Tomishima, Tadato Yamagata | 1999-06-08 |
| 5539344 | Phase-locked circuit and interated circuit device | — | 1996-07-23 |