Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8178722 | Method for producing theanine | Fumio Tonegawa | 2012-05-15 |
| 7656984 | Circuits and methods for recovering a clock signal | Nyun-Tae Kim, Ki Hong Kim, Shu Wang, Mi Jeong Kim | 2010-02-02 |
| 7050524 | Half-rate clock and data recovery circuit | Jun Takasoh | 2006-05-23 |
| 6960702 | Disposable absorbent article employing odor reduction layer containing metalphthalocyanine material | Yoshihisa Kawakami, Vijay Rajagopalan, Ebranim Rezai | 2005-11-01 |
| 6677676 | Semiconductor device having steady substrate potential | Yoshiki Wada | 2004-01-13 |
| 6639446 | High linearity, high gain mixer circuit | Hiroshi Komurasaki, Hisayasu Sato | 2003-10-28 |
| 6477186 | Fast operating multiplexer | Toru Nakura | 2002-11-05 |
| 6472712 | Semiconductor device with reduced transistor leakage current | Toru Nakura | 2002-10-29 |
| 6433620 | Silicon-on-insulator CMOS circuit | Koichiro Mashiko, Yoshiki Wada | 2002-08-13 |
| 6249157 | Synchronous frequency dividing circuit | Toru Nakura | 2001-06-19 |
| 6242786 | SOI Semiconductor device with field shield electrode | Yoshiki Wada, Hirotada Kuriyama, Koichiro Mashiko, Hiroaki Suzuki | 2001-06-05 |
| 6225846 | Body voltage controlled semiconductor integrated circuit | Yoshiki Wada | 2001-05-01 |
| 6208494 | Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge | Toru Nakura | 2001-03-27 |
| 6177826 | Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate | Koichiro Mashiko, Yoshiki Wada | 2001-01-23 |
| 6127892 | Amplification circuit | Hiroshi Komurasaki, Hisayasu Satoh | 2000-10-03 |
| 6104214 | Current mode logic circuit, source follower circuit, and flip flop circuit | Yuuichi Hirano, Yoshiki Wada | 2000-08-15 |
| 6100565 | Semiconductor integrated circuit device with operation in partial depletion type mode and perfect depletion type mode | — | 2000-08-08 |
| 6101233 | Counter circuit | Toru Nakura | 2000-08-08 |
| 6084255 | Gate array semiconductor device | Takanori Hirota, Yoshiki Wada, Koichiro Mashiko | 2000-07-04 |
| 6005422 | Semiconductor integrated circuit and consumed power reducing method | Hiroyuki Morinaka, Hiroshi Makino, Koichiro Mashiko | 1999-12-21 |
| 5994935 | Latch circuit and flip-flop circuit reduced in power consumption | Koichiro Mashiko, Yoshiki Wada | 1999-11-30 |
| 5891765 | Method of fabricating a gate array semiconductor integrated circuit device | Hiroyuki Morinaka, Koichiro Mashiko | 1999-04-06 |
| 5892382 | Current mode logic circuit, source follower circuit and flip flop circuit | Yuuichi Hirano, Yoshiki Wada | 1999-04-06 |
| 5859800 | Data holding circuit and buffer circuit | Hiroyuki Morinaka, Koichiro Mashiko | 1999-01-12 |
| 5856386 | Process for crystal nucleation of crystalline thermoplastic resin | Hideki Sakai, Mikio Nakagawa, Tetsuji Kasai, Masao Maeda, Yukiharu Yamada +3 more | 1999-01-05 |