Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9564965 | Signal monitoring apparatus, signal transmitting/receiving apparatus, and communication apparatus | — | 2017-02-07 |
| 6677676 | Semiconductor device having steady substrate potential | Kimio Ueda | 2004-01-13 |
| 6518790 | Semiconductor integrated circuit having circuit for transmitting input signal | Harufusa Kondoh | 2003-02-11 |
| 6500722 | Inductor recognition method, layout inspection method, computer readable recording medium in which a layout inspection program is recorded and process for a semiconductor device | Hiroshi Komurasaki, Shigenobu Maeda, Shuji Yoshida | 2002-12-31 |
| 6433620 | Silicon-on-insulator CMOS circuit | Koichiro Mashiko, Kimio Ueda | 2002-08-13 |
| 6372481 | Instant dry yeast for use in frozen dough-baking process | Setsu Hitokoto, Kazuhiro Hamada, Masayasu Ando, Yasuo Suzuki | 2002-04-16 |
| 6242786 | SOI Semiconductor device with field shield electrode | Hirotada Kuriyama, Kimio Ueda, Koichiro Mashiko, Hiroaki Suzuki | 2001-06-05 |
| 6225846 | Body voltage controlled semiconductor integrated circuit | Kimio Ueda | 2001-05-01 |
| 6177826 | Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate | Koichiro Mashiko, Kimio Ueda | 2001-01-23 |
| 6104214 | Current mode logic circuit, source follower circuit, and flip flop circuit | Kimio Ueda, Yuuichi Hirano | 2000-08-15 |
| 6084255 | Gate array semiconductor device | Kimio Ueda, Takanori Hirota, Koichiro Mashiko | 2000-07-04 |
| 5994935 | Latch circuit and flip-flop circuit reduced in power consumption | Kimio Ueda, Koichiro Mashiko | 1999-11-30 |
| 5934983 | Double-side grinding method and double-side grinder | Yoshihiro Hara, Norihide Tokunaga, Gisaburo Kondoh | 1999-08-10 |
| 5892382 | Current mode logic circuit, source follower circuit and flip flop circuit | Kimio Ueda, Yuuichi Hirano | 1999-04-06 |