Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10486231 | Silver-coated copper powder | Kentaro Ochi | 2019-11-26 |
| 10357824 | Dendritic silver powder | Yasunari Wakimori, Kentaro Ochi | 2019-07-23 |
| 6820107 | Square root extraction circuit and floating-point square root extraction device | Hiroyuki Kawai, Robert Streitenberger, Yoshitsugu Inoue | 2004-11-16 |
| 6375784 | Method of manufacturing reversible heat-sensitive recording medium and reversible heat-sensitive recording medium manufactured thereby | Haruhiko Ohsawa, Makibi Nakanishi, Junpei Nakagawa, Koh Fujii | 2002-04-23 |
| 6148318 | Square root extraction circuit and floating-point square root extraction device | Hiroyuki Kawai, Robert Streitenberger, Yoshitsugu Inoue | 2000-11-14 |
| 6005422 | Semiconductor integrated circuit and consumed power reducing method | Hiroshi Makino, Kimio Ueda, Koichiro Mashiko | 1999-12-21 |
| 6001518 | Reversible heat-sensitive recording material with high color development and image stabilization capabilities | Haruhiko Ohsawa, Shin Koizumi, Minoru Fujita | 1999-12-14 |
| 5891765 | Method of fabricating a gate array semiconductor integrated circuit device | Kimio Ueda, Koichiro Mashiko | 1999-04-06 |
| 5859800 | Data holding circuit and buffer circuit | Kimio Ueda, Koichiro Mashiko | 1999-01-12 |
| 5781062 | Semiconductor integrated circuit | Koichiro Mashiko, Kimio Ueda, Hiroaki Suzuki | 1998-07-14 |
| 5747847 | Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit | Kimio Ueda, Koichiro Mashiko | 1998-05-05 |
| 5646555 | Pipeline structure using positive edge and negative edge flip-flops to decrease the size of a logic block | — | 1997-07-08 |
| 5633524 | Gate array semiconductor integrated circuit device | Kimio Ueda, Koichiro Mashiko | 1997-05-27 |
| 5631860 | Carry Selecting system type adder | — | 1997-05-20 |