Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7054979 | Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports | Hiroyuki Kawai, Yoshitsugu Inoue, Junko Kobara | 2006-05-30 |
| 6820107 | Square root extraction circuit and floating-point square root extraction device | Hiroyuki Kawai, Yoshitsugu Inoue, Hiroyuki Morinaka | 2004-11-16 |
| 6795075 | Graphic processor having multiple geometric operation units and method of processing data thereby | Hiroyuki Kawai, Junko Kobara, Yoshitsugu Inoue, Keijiro Yoshimatsu | 2004-09-21 |
| 6711601 | Logarithmic arithmetic unit avoiding division as far as predetermined arithmetic precision is guaranteed | Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara | 2004-03-23 |
| 6697889 | First-in first-out data transfer control device having a plurality of banks | Junko Kobara, Hiroyuki Kawai, Yoshitsugu Inoue | 2004-02-24 |
| 6675251 | Bridge device for connecting multiple devices to one slot | Hiroyuki Kawai, Yoshitsugu Inoue, Junko Kobara | 2004-01-06 |
| 6603481 | Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel | Hiroyuki Kawai, Yoshitsugu Inoue, Keijiro Yoshimatsu, Junko Kobara, Hiroyasu Negishi | 2003-08-05 |
| 6581087 | Floating point adder capable of rapid clip-code generation | Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara | 2003-06-17 |
| 6480873 | Power operation device | Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara, Keijiro Yoshimatsu, Hiroyasu Negishi | 2002-11-12 |
| 6442627 | Output FIFO data transfer control device | Hiroyasu Negishi, Junko Kobara, Yoshitsugu Inoue, Hiroyuki Kawai, Keijiro Yoshimatsu +1 more | 2002-08-27 |
| 6272582 | PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device | Hiroyuki Kawai | 2001-08-07 |
| 6148318 | Square root extraction circuit and floating-point square root extraction device | Hiroyuki Kawai, Yoshitsugu Inoue, Hiroyuki Morinaka | 2000-11-14 |
| 5729758 | SIMD processor operating with a plurality of parallel processing elements in synchronization | Yoshitsugu Inoue, Hiroyuki Kawai | 1998-03-17 |
| 5715436 | Image processing LSI circuit with image preprocessing, feature extraction and matching | Hiroyuki Kawai, Yoshitsugu Inoue | 1998-02-03 |
| 5657485 | Program control operation to execute a loop processing not immediately following a loop instruction | Hiroyuki Kawai, Yoshitsugu Inoue | 1997-08-12 |