Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6856537 | Thin film magnetic memory device having dummy cell | Takaharu Tsuji, Tsukasa Ooishi | 2005-02-15 |
| 6842366 | Thin film magnetic memory device executing self-reference type data read | Tsukasa Ooishi, Hideto Hidaka | 2005-01-11 |
| 6835226 | Negative electrode active material, method of producing the same, and nonaqueous electrolyte cell | Takatomo Nishino, Hiroshi Inoue | 2004-12-28 |
| 6791876 | Thin-film magnetic memory device suppressing parasitic capacitance applied to data line or the like | Takaharu Tsuji, Hideto Hidaka | 2004-09-14 |
| 6788569 | Thin film magnetic memory device reducing a charging time of a data line in a data read operation | Hideto Hidaka, Tsukasa Ooishi | 2004-09-07 |
| 6781873 | Non-volatile memory device capable of generating accurate reference current for determination | Masatoshi Ishikawa | 2004-08-24 |
| 6778445 | Pipeline nonvolatile memory device with multi-bit parallel read and write suitable for cache memory. | Tsukasa Ooishi | 2004-08-17 |
| 6762953 | Nonvolatile memory device with sense amplifier securing reading margin | Hideto Hidaka, Tsukasa Ooishi | 2004-07-13 |
| 6738285 | Thin film magnetic memory device with high-accuracy data read structure having a reduced number of circuit elements | Hideto Hidaka, Tsukasa Ooishi | 2004-05-18 |
| 6728122 | Semiconductor memory device capable of rewriting data signal | Tsukasa Ooishi | 2004-04-27 |
| 6707737 | Memory system capable of switching between a reference voltage for normal operation and a reference voltage for burn-in test | — | 2004-03-16 |
| 6679925 | Methods of manufacturing negative material and secondary battery | Hiroshi Imoto, Atsuo Omaru | 2004-01-20 |
| 6677080 | Non-aqueous electrolyte secondary cell | Atsuo Omaru | 2004-01-13 |
| 6603685 | Semiconductor integrated circuit device capable of ensuring reliability of transistor driving high voltage | Hideto Hidaka, Tsukasa Ooishi | 2003-08-05 |
| 6597040 | Semiconductor device having MOS transistor for coupling two signal lines | Masatoshi Ishikawa | 2003-07-22 |
| 6549445 | Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof | Tsukasa Ooishi | 2003-04-15 |
| 6466509 | Semiconductor memory device having a column select line transmitting a column select signal | Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa +3 more | 2002-10-15 |
| 6463098 | Data transfer circuit transferring 2-bit data through 4 data lines | Masatoshi Ishikawa | 2002-10-08 |
| 6452976 | Data transfer circuit with reduced current consumption | Masatoshi Ishikawa | 2002-09-17 |
| 6445633 | Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit | Mitsue Takahashi | 2002-09-03 |
| 6430091 | Semiconductor memory device having reduced current consumption at internal boosted potential | — | 2002-08-06 |
| 6411560 | Semiconductor memory device capable of reducing leakage current flowing into substrate | Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa +3 more | 2002-06-25 |
| 6400632 | Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall | Hideto Hidaka, Tsukasa Ooishi, Shigeki Tomishima, Hiroshi Kato | 2002-06-04 |
| 6385125 | Synchronous semiconductor integrated circuit device capable of test time reduction | Tsukasa Ooishi, Shigeki Tomishima, Yutaka Komai | 2002-05-07 |
| 6384674 | Semiconductor device having hierarchical power supply line structure improved in operating speed | Tsukasa Ooishi, Shigeki Tomishima, Masatoshi Ishikawa, Hideto Hidaka, Takaharu Tsuji | 2002-05-07 |