Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229541 | Dual architecture function pointers having consistent reference addresses | Pedro Miguel Sequeira De Justo Teixeira, Jon Robert Berry, Russell Charles Hadley, James D. Cleary, Clarence Siu Yeen Dang | 2025-02-18 |
| 11720335 | Hybrid binaries supporting code stream folding | Pedro Miguel Sequeira De Justo Teixeira, Jon Robert Berry, Russell Charles Hadley, James D. Cleary, Clarence Siu Yeen Dang | 2023-08-08 |
| 11593113 | Widening memory access to an aligned address for unaligned memory operations | Arun U. Kishan, Pedro Miguel Sequeira De Justo Teixeira | 2023-02-28 |
| 11403100 | Dual architecture function pointers having consistent reference addresses | Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James D. Cleary, Jon Robert Berry +2 more | 2022-08-02 |
| 11231918 | Native emulation compatible application binary interface for supporting emulation of foreign code | Pedro Miguel Sequeira De Justo Teixeira, Jon Robert Berry, Russell Charles Hadley, James D. Cleary, Clarence Siu Yeen Dang | 2022-01-25 |
| 11163575 | Widening memory access to an aligned address for unaligned memory operations | Arun U. Kishan, Pedro Miguel Sequeira De Justo Teixeira | 2021-11-02 |
| 11042422 | Hybrid binaries supporting code stream folding | Pavlo Lebedynskiy, Pedro Miguel Sequeira De Justo Teixeira, Jon Robert Berry, Clarence Siu Yeen Dang, Tiansheng Tan +5 more | 2021-06-22 |
| 10481999 | Partial process recording | Jordi Mola, Juan Carlos Arevalo Baeza | 2019-11-19 |
| 10261785 | Arithmetic lazy flags representation for emulation | — | 2019-04-16 |
| 10198341 | Parallel replay of executable code | Jordi Mola, Juan Carlos Arevalo Baeza, Ivette Carreras | 2019-02-05 |
| 9934126 | Indexing a trace by insertion of reverse lookup data structures | Jordi Mola, Juan Carlos Arevalo Baeza | 2018-04-03 |
| 9104485 | CPU sharing techniques | Pradeep Vincent | 2015-08-11 |
| 9043553 | Leveraging transactional memory hardware to accelerate virtualization and emulation | Martin Taillefer, Bruno Silva | 2015-05-26 |
| 8935699 | CPU sharing techniques | Pradeep Vincent | 2015-01-13 |
| 8473921 | Debugging mechanisms in a cache-based memory isolation system | Martin Taillefer, Ali-Reza Adl-Tabatabai, Gad Sheaffer, Peter Lachner, Richard Wurdack +1 more | 2013-06-25 |
| 8356166 | Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers | Ali-Reza Adl-Tabatabai, Bratin Saha, Gad Sheaffer, Vadim Bassin, Robert Geva +3 more | 2013-01-15 |
| 8266387 | Leveraging transactional memory hardware to accelerate virtualization emulation | Martin Taillefer, Bruno Silva | 2012-09-11 |
| 8176253 | Leveraging transactional memory hardware to accelerate virtualization and emulation | Martin Taillefer, Bruno Silva | 2012-05-08 |
| 7752028 | Signed/unsigned integer guest compare instructions using unsigned host compare instructions for precise architecture emulation | Jens Troeger | 2010-07-06 |
| 7620938 | Compressed program recording | Andrew James Edwards, Ho-Yuen Chau, Ronald C. Murray, Sanjay Bhansali, Stuart de Jong +2 more | 2009-11-17 |