Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9667237 | Hardware delay compensation in digital phase locked loop | Qu Gary Jin, Krste Mitric, Cathy Zhang, Gabriel Rusaneanu, Wenbao Wang | 2017-05-30 |
| 9647674 | Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers | Krste Mitric, Gabriel Rusaneanu | 2017-05-09 |
| 9634675 | Phase locked loop with jump-free holdover mode | Krste Mitric | 2017-04-25 |
| 9595972 | Digital phase locked loop arrangement with master clock redundancy | Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Mark A Warriner | 2017-03-14 |
| 9584138 | Phase locked loop with accurate alignment among output clocks | Krste Mitric, Qu Gary Jin, Guohui Situ, Changhui Zhang, Richard Geiss | 2017-02-28 |
| 9124415 | PLL glitchless phase adjustment system | David Colby, Joep De Rijk, Tanmay Zargar | 2015-09-01 |
| 9094185 | Phase locked loop with the ability to accurately apply phase offset corrections while maintaining the loop filter characteristics | Krste Mitric, Slobodan Milijevic, Tanmay Zargar, David Colby | 2015-07-28 |
| 8907706 | Phase locked loop with simultaneous locking to low and high frequency clocks | Krste Mitric, Tanmay Zargar, David Colby, Cathy Zhang, Robertus Laurentius van der Valk | 2014-12-09 |