Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10069503 | Method of speeding up output alignment in a digital phase locked loop | Changhui Zhang, Qu Gary Jin, Kamran Rahbar | 2018-09-04 |
| 10002090 | Method for improving the performance of synchronous serial interfaces | Gabriel Rusaneanu, Wenbao Wang | 2018-06-19 |
| 9858134 | Low latency digital clock fault detector | Mark L. Thrower | 2018-01-02 |
| 9595972 | Digital phase locked loop arrangement with master clock redundancy | Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Paul H. L. M. Schram | 2017-03-14 |