Issued Patents All Time
Showing 51–75 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8237474 | Delay line off-state control with power reduction | Debra M. Bell | 2012-08-07 |
| 8217694 | Method and apparatus for synchronizing with a clock signal | Gary M. Johnson | 2012-07-10 |
| 8164368 | Power savings mode for memory systems | Greg A. Blodgett | 2012-04-24 |
| 8149034 | Delay lines, methods for delaying a signal, and delay lock loops | — | 2012-04-03 |
| 8073890 | Continuous high-frequency event filter | Kang-Yong Kim | 2011-12-06 |
| 8018261 | Clock generator and methods using closed loop duty cycle correction | Eric Becker, Eric Booth | 2011-09-13 |
| 7990802 | Selective edge phase mixing | Eric Booth | 2011-08-02 |
| 7973577 | Control of a variable delay line using line entry point to modify line power supply voltage | Kang-Yong Kim, Jongtae Kwak | 2011-07-05 |
| 7945800 | Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch | Gary M. Johnson | 2011-05-17 |
| 7936199 | Apparatus and method for external to internal clock generation | Michael V. Ho, Scott E. Smith | 2011-05-03 |
| 7898308 | Apparatus and method for trimming static delay of a synchronizing circuit | Kang-Yong Kim | 2011-03-01 |
| 7872507 | Delay lines, methods for delaying a signal, and delay lock loops | — | 2011-01-18 |
| 7855585 | Local coarse delay units | Kang-Yong Kim | 2010-12-21 |
| 7812657 | Methods and apparatus for synchronizing with a clock signal | Gary M. Johnson | 2010-10-12 |
| 7791388 | Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit | — | 2010-09-07 |
| 7728639 | Trimmable delay locked loop circuitry with improved initialization characteristics | Eric Booth, Jongtae Kwak | 2010-06-01 |
| 7701788 | Apparatus and method for selectively configuring a memory device using a bi-stable relay | — | 2010-04-20 |
| 7671647 | Apparatus and method for trimming static delay of a synchronizing circuit | Kang-Yong Kim | 2010-03-02 |
| 7609583 | Selective edge phase mixing | Eric Booth | 2009-10-27 |
| 7583115 | Delay line off-state control with power reduction | Debra M. Bell | 2009-09-01 |
| 7541851 | Control of a variable delay line using line entry point to modify line power supply voltage | Kang-Yong Kim, Jongtae Kwak | 2009-06-02 |
| 7525354 | Local coarse delay units | Kang-Yong Kim | 2009-04-28 |
| 7471130 | Graduated delay line for increased clock skew correction circuit operating range | Gary M. Johnson | 2008-12-30 |
| 7443216 | Trimmable delay locked loop circuitry with improved initialization characteristics | Eric Booth, Jongtae Kwak | 2008-10-28 |
| 7423462 | Clock capture in clock synchronization circuitry | Adrian J. Drexler, Debra M. Bell, Seong-Hoon Lee | 2008-09-09 |