Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6750497 | High-speed transparent refresh DRAM-based memory cell | — | 2004-06-15 |
| 6690606 | Asynchronous interface circuit and method for a pseudo-static memory device | Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck | 2004-02-10 |
| 6664799 | Method and apparatus for enabling a digital memory tester to read the frequency of a free running oscillator | — | 2003-12-16 |
| 6538466 | Buffer with stable trip point | — | 2003-03-25 |
| 6445645 | Random access memory having independent read port and write port and process for writing to and reading from the same | Mathew R. Arcoleo, Cathal G. Phelan, Ashish Pancholy | 2002-09-03 |
| 6385128 | Random access memory having a read/write address bus and process for writing to and reading from the same | Mathew R. Arcoleo, Cathal G. Phelan, Ashish Pancholy | 2002-05-07 |
| 6292403 | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Ashish Pancholy, Cathal G. Phelan | 2001-09-18 |
| 6278295 | Buffer with stable trip point | — | 2001-08-21 |
| 6262937 | Synchronous random access memory having a read/write address bus and process for writing to and reading from the same | Mathew R. Arcoleo, Cathal G. Phelan, Ashish Pancholy | 2001-07-17 |
| 6262936 | Random access memory having independent read port and write port and process for writing to and reading from the same | Mathew R. Arcoleo, Cathal G. Phelan, Ashish Pancholy | 2001-07-17 |
| 6181621 | Threshold voltage mismatch compensated sense amplifier for SRAM memory arrays | — | 2001-01-30 |
| 6100560 | Nonvolatile cell | — | 2000-08-08 |
| 6097222 | Symmetrical NOR gates | — | 2000-08-01 |
| 6069839 | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Ashish Pancholy, Cathal G. Phelan | 2000-05-30 |
| 5936973 | Test mode latching scheme | A. Majid Farmanfarmaian, Sammy Cheung, Mark Rouse | 1999-08-10 |
| 5889416 | Symmetrical nand gates | — | 1999-03-30 |