ML

Murong Lang

Micron: 69 patents #232 of 6,345Top 4%
ST Sandisk Technologies: 3 patents #751 of 2,224Top 35%
📍 San Jose, CA: #511 of 32,062 inventorsTop 2%
🗺 California: #4,195 of 386,348 inventorsTop 2%
Overall (All Time): #27,412 of 4,157,543Top 1%
72
Patents All Time

Issued Patents All Time

Showing 26–50 of 72 patents

Patent #TitleCo-InventorsDate
12014049 Adaptive sensing time for memory operations Yu-Chung Lien, Zhenming Zhou, Ching-Huang Lu 2024-06-18
12014050 Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system Zhenming Zhou, Ching-Huang Lu 2024-06-18
12009027 Refresh of neighboring memory cells based on read status Li-Te Chang, Zhenming Zhou 2024-06-11
11977480 Scaling factors for media management operations at a memory device Mikai Chen, Zhenlei Shen, Zhenming Zhou 2024-05-07
11966591 Apparatus with read level management and methods for operating the same Tingjun Xie, Fangfang Zhu, Zhenming Zhou, Jiangli Zhu 2024-04-23
11960745 Empty page scan operations adjustment Peng Zhang, Christina Papagianni, Zhenming Zhou 2024-04-16
11947831 Adaptive enhanced corrective read based on write and read temperature Zhenming Zhou, Ching-Huang Lu, Nagendra Prasad Ganesh Rao 2024-04-02
11929127 Selective data pattern write scrub for a memory system Zhongguang Xu, Zhenming Zhou 2024-03-12
11923001 Managing the programming of an open translation unit Zhenming Zhou, Jian Huang, Tingjun Xie, Jiangli Zhu, Nagendra Prasad Ganesh Rao +1 more 2024-03-05
11914889 Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system Tingjun Xie, Wei Wang, Frederick Adi, Zhenming Zhou, Jiangli Zhu 2024-02-27
11901014 Partial block handling in a non-volatile memory device Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Ugo Russo +1 more 2024-02-13
11881284 Open translation unit management using an adaptive read threshold Zhenming Zhou, Jian Huang, Zhongguang Xu, Jiangli Zhu 2024-01-23
11861178 Managing a hybrid error recovery process in a memory sub-system Zhongguang Xu, Jian Huang, Tingjun Xie, Zhenming Zhou 2024-01-02
11854644 Performing select gate integrity checks to identify and invalidate defective blocks Zhongguang Xu, Zhenlei Shen 2023-12-26
11776611 Managing write disturb for units of a memory device using weighted write disturb counts Mikai Chen, Zhenming Zhou, Zhenlei Shen 2023-10-03
11762589 Dynamic read-level thresholds in memory systems Zhongguang Xu, Tingjun Xie, Zhenming Zhou 2023-09-19
11763914 Adapting an error recovery process in a memory sub-system Zhongguang Xu, Zhenming Zhou 2023-09-19
11756597 Power-on read demarcation voltage optimization Mikai Chen, Zhenlei Shen, Zhenming Zhou 2023-09-12
11742029 Adjusting read-level thresholds based on write-to-write delay Zhongguang Xu, Tingjun Xie, Zhenming Zhou 2023-08-29
11740959 Dynamic voltage setting optimization during lifetime of a memory device Zhongguang Xu, Zhenming Zhou 2023-08-29
11742053 Managing execution of a scrub operation in view of an operating characteristic of a memory subsystem Zhongguang Xu, Zhenming Zhou 2023-08-29
11735284 Optimized seasoning trim values based on form factors in memory sub-system manufacturing Tingjun Xie, Zhenming Zhou 2023-08-22
11721381 Performing refresh operations of a memory device according to a dynamic refresh frequency Li-Te Chang, Zhongguang Xu, Zhenming Zhou 2023-08-08
11709602 Adaptively performing media management operations on a memory device Mikai Chen, Zhenming Zhou 2023-07-25
11698731 Performance throttling based on power-off time Zhenming Zhou 2023-07-11