Issued Patents All Time
Showing 126–150 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5548132 | Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions | Shubneesh Batra, Sanjay Banerjee, John Damiano, Jr. | 1996-08-20 |
| 5541137 | Method of forming improved contacts from polysilicon to silicon or other polysilicon layers | Shubneesh Batra, Charles H. Dennison | 1996-07-30 |
| 5493130 | Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers | Charles H. Dennison | 1996-02-20 |
| 5491107 | Semiconductor processing method for providing large grain polysilicon films | Charles L. Turner | 1996-02-13 |
| 5434103 | Method of forming an electrical connection | Charles H. Dennison | 1995-07-18 |
| 5422499 | Sixteen megabit static random access memory (SRAM) cell | — | 1995-06-06 |
| 5420061 | Method for improving latchup immunity in a dual-polysilicon gate process | — | 1995-05-30 |
| 5411909 | Method of forming a planar thin film transistor | Charles H. Dennison | 1995-05-02 |
| 5405788 | Method for forming and tailoring the electrical characteristics of semiconductor devices | Charles H. Dennison, Howard E. Rhodes, Tyler Lowrey | 1995-04-11 |
| 5392245 | Redundancy elements using thin film transistors (TFTs) | — | 1995-02-21 |
| 5390143 | Non-volatile static memory devices and operational methods | — | 1995-02-14 |
| 5385854 | Method of forming a self-aligned low density drain inverted thin film transistor | Shubneesh Batra | 1995-01-31 |
| 5348899 | Method of fabricating a bottom and top gated thin film transistor | Charles H. Dennison | 1994-09-20 |
| 5346836 | Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects | Steve V. Cole, Tyler Lowrey | 1994-09-13 |
| 5334862 | Thin film transistor (TFT) loads formed in recessed plugs | Charles H. Dennison | 1994-08-02 |
| 5298792 | Integrated circuit device with bi-level contact landing pads | — | 1994-03-29 |
| 5292676 | Self-aligned low resistance buried contact process | — | 1994-03-08 |
| 5286663 | Methods for producing thin film transistor having a diode shunt | — | 1994-02-15 |
| 5275965 | Trench isolation using gated sidewalls | — | 1994-01-04 |
| 5266523 | Method of forming self-aligned contacts using the local oxidation of silicon | — | 1993-11-30 |
| 5246876 | Low cost polysilicon active P-channel load | — | 1993-09-21 |
| 5241206 | Self-aligned vertical intrinsic resistance | Ruojia Lee | 1993-08-31 |
| 5232865 | Method of fabricating vertically integrated oxygen-implanted polysilicon resistor | Roger Lee | 1993-08-03 |
| 5215932 | Self-aligned 3-dimensional PMOS devices without selective EPI | — | 1993-06-01 |
| 5214295 | Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inverters | — | 1993-05-25 |