Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6751149 | Magnetic tunneling junction antifuse device | Mark E. Tuttle, Glen E. Hush | 2004-06-15 |
| 6725414 | Error correction chip for memory applications | — | 2004-04-20 |
| 6574137 | Single ended row select for a MRAM device | Tom Voshell | 2003-06-03 |
| 6424584 | Redundancy antifuse bank for a memory device | — | 2002-07-23 |
| 6320816 | Column select latch for SDRAM | Jeffrey P. Wright | 2001-11-20 |
| 6301175 | Memory device with single-ended sensing and low voltage pre-charge | Brian M. Shirley | 2001-10-09 |
| 6292417 | Memory device with reduced bit line pre-charge voltage | — | 2001-09-18 |
| 6282689 | Error correction chip for memory applications | — | 2001-08-28 |
| 6281709 | Fuse option for multiple logic families on the same die | — | 2001-08-28 |
| 6265775 | Flip chip technique for chip assembly | — | 2001-07-24 |
| 6252293 | Laser antifuse using gate capacitor | Manny K. F. Ma | 2001-06-26 |
| 6246632 | Column decode circuits and apparatus | Jeffrey P. Wright | 2001-06-12 |
| 6221753 | Flip chip technique for chip assembly | — | 2001-04-24 |
| 6205080 | Column decode circuits and apparatus | Jeffrey P. Wright | 2001-03-20 |
| 6201740 | Cache memories using DRAM cells with high-speed data path | Paul S. Zagar | 2001-03-13 |
| 6182262 | Multi bank test mode for memory devices | — | 2001-01-30 |
| 6044433 | DRAM cache | Paul S. Zagar | 2000-03-28 |
| 6004825 | Method for making three dimensional ferroelectric memory | — | 1999-12-21 |
| 5999439 | Ferroelectric memory using ferroelectric reference cells | — | 1999-12-07 |
| 5996106 | Multi bank test mode for memory devices | — | 1999-11-30 |
| 5978309 | Selectively enabled memory array access signals | Jeffrey P. Wright | 1999-11-02 |
| 5969380 | Three dimensional ferroelectric memory | — | 1999-10-19 |
| 5953739 | Synchronous DRAM cache using write signal to determine single or burst write | Paul S. Zagar | 1999-09-14 |
| 5933372 | Data path for high speed high bandwidth DRAM | Paul S. Zagar | 1999-08-03 |
| 5926034 | Fuse option for multiple logic families on the same die | — | 1999-07-20 |