Issued Patents All Time
Showing 201–225 of 236 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6260154 | Apparatus for aligning clock and data signals received from a RAM | — | 2001-07-10 |
| 6252612 | Accelerated graphics port for multiple memory controller computer system | — | 2001-06-26 |
| 6253276 | Apparatus for adaptive decoding of memory addresses | — | 2001-06-26 |
| 6219765 | Memory paging control apparatus | — | 2001-04-17 |
| 6219764 | Memory paging control method | — | 2001-04-17 |
| 6212598 | Controlling a paging policy based on a requestor characteristic | — | 2001-04-03 |
| 6202133 | Method of processing memory transactions in a computer system having dual system memories and memory controllers | — | 2001-03-13 |
| 6199138 | Controlling a paging policy based on a requestor characteristic | — | 2001-03-06 |
| 6185664 | Method for providing additional latency for synchronously accessed memory | — | 2001-02-06 |
| 6181638 | Method for receiving data from a synchronous random access memory | — | 2001-01-30 |
| 6163852 | Apparatus for receiving data from a synchronous random access memory | — | 2000-12-19 |
| 6157398 | Method of implementing an accelerated graphics port for a multiple memory controller computer system | — | 2000-12-05 |
| 6108795 | Method for aligning clock and data signals received from a RAM | — | 2000-08-22 |
| 6101612 | Apparatus for aligning clock and data signals received from a RAM | — | 2000-08-08 |
| 6085339 | System for memory error handling | — | 2000-07-04 |
| 6076182 | Memory fault correction system and method | — | 2000-06-13 |
| 6052798 | System and method for remapping defective memory locations | — | 2000-04-18 |
| 6049855 | Segmented memory system employing different interleaving scheme for each different memory segment | — | 2000-04-11 |
| 6035432 | System for remapping defective memory bit sets | — | 2000-03-07 |
| 6031787 | Apparatus for providing additional latency for synchronously accessed memory | — | 2000-02-29 |
| 6018792 | Apparatus for performing a low latency memory read with concurrent snoop | James W. Meyer, Jeffrey R. Brown | 2000-01-25 |
| 5991855 | Low latency memory read with concurrent pipe lined snoops | James W. Meyer, Jeffrey R. Brown | 1999-11-23 |
| 5974564 | Method for remapping defective memory bit sets to non-defective memory bit sets | — | 1999-10-26 |
| 5953743 | Method for accelerating memory bandwidth | — | 1999-09-14 |
| 5950229 | System for accelerating memory bandwidth | — | 1999-09-07 |