Issued Patents All Time
Showing 51–75 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6777715 | Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same | Kie Y. Ahn, Leonard Forbes | 2004-08-17 |
| 6723577 | Method of forming an optical fiber interconnect through a semiconductor wafer | Kie Y. Ahn, Leonard Forbes | 2004-04-20 |
| 6709978 | Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer | Kie Y. Ahn, Leonard Forbes | 2004-03-23 |
| 6706597 | Method for textured surfaces in floating gate tunneling oxide devices | Leonard Forbes | 2004-03-16 |
| 6657370 | Microcavity discharge device | — | 2003-12-02 |
| 6630713 | Low temperature silicon wafer bond process with bulk material bond strength | — | 2003-10-07 |
| 6602653 | Conductive material patterning methods | Alan R. Reinberg | 2003-08-05 |
| 6593656 | Multilevel copper interconnects for ultra large scale integration | Kie Y. Ahn | 2003-07-15 |
| 6582512 | Method of forming three-dimensional photonic band structures in solid materials | Kevin G. Donohoe | 2003-06-24 |
| 6579803 | Removal of copper oxides from integrated interconnects | Alan R. Reinberg | 2003-06-17 |
| 6579738 | Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials | Paul A. Farrar | 2003-06-17 |
| 6545314 | Memory using insulator traps | Leonard Forbes | 2003-04-08 |
| 6526191 | Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same | Kie Y. Ahn, Leonard Forbes | 2003-02-25 |
| 6518615 | Method and structure for high capacitance memory cells | Leonard Forbes, Kie Y. Ahn | 2003-02-11 |
| 6496370 | Structure and method for an electronic assembly | Leonard Forbes, Kie Y. Ahn | 2002-12-17 |
| 6476441 | Method and structure for textured surfaces in floating gate tunneling oxide devices | Leonard Forbes | 2002-11-05 |
| 6456535 | Dynamic flash memory cells with ultra thin tunnel oxides | Leonard Forbes, Luan C. Tran, Alan R. Reinberg, Kie Y. Ahn, Paul A. Farrar +2 more | 2002-09-24 |
| 6451685 | Method for multilevel copper interconnects for ultra large scale integration | Kie Y. Ahn | 2002-09-17 |
| 6423613 | Low temperature silicon wafer bond process with bulk material bond strength | — | 2002-07-23 |
| 6383924 | Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials | Paul A. Farrar | 2002-05-07 |
| 6356500 | Reduced power DRAM device and method | Eugene H. Cloud, Kie Y. Ahn, Leonard Forbes, Paul A. Farrar, Kevin G. Donohoe +3 more | 2002-03-12 |
| 6351411 | Memory using insulator traps | Leonard Forbes | 2002-02-26 |
| 6348125 | Removal of copper oxides from integrated interconnects | Alan R. Reinberg | 2002-02-19 |
| 6331465 | Alternate method and structure for improved floating gate tunneling devices using textured surface | Leonard Forbes | 2001-12-18 |
| 6313531 | Coaxial integrated circuitry interconnect lines, and integrated circuitry | Kie Y. Ahn, Leonard Forbes | 2001-11-06 |