Issued Patents All Time
Showing 126–140 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5903509 | Memory device with multiple internal banks and staggered command execution | Kevin J. Ryan | 1999-05-11 |
| 5895962 | Structure and a method for storing information in a semiconductor device | Hua Zheng, Michael A. Shore, Todd A. Merritt | 1999-04-20 |
| 5883853 | Clock frequency detector for a synchronous memory device | Hua Zheng | 1999-03-16 |
| 5835441 | Column select latch for SDRAM | Mirmajid Seyyedy | 1998-11-10 |
| 5805505 | Circuit and method for converting a pair of input signals into a level-limited output signal | Hua Zheng | 1998-09-08 |
| 5796266 | Circuit and a method for configuring pad connections in an integrated device | Hua Zheng | 1998-08-18 |
| 5784332 | Clock frequency detector for a synchronous memory device | Hua Zheng | 1998-07-21 |
| 5748542 | Circuit and method for providing a substantially constant time delay over a range of supply voltages | Hua Zheng | 1998-05-05 |
| 5748551 | Memory device with multiple internal banks and staggered command execution | Kevin J. Ryan | 1998-05-05 |
| 5721658 | Input/output electrostatic discharge protection for devices with multiple individual power groups | Manny K. F. Ma | 1998-02-24 |
| 5673233 | Synchronous memory allowing early read command in write to read transitions | Hua Zheng | 1997-09-30 |
| 5627791 | Multiple bank memory with auto refresh to specified bank | Hua Zheng | 1997-05-06 |
| 5612630 | Asynchronous self-adjusting input circuit | Eugene H. Cloud | 1997-03-18 |
| 5587961 | Synchronous memory allowing early read command in write to read transitions | Hua Zheng | 1996-12-24 |
| 5159273 | Tri-state bus driver to support reconfigurable fault tolerant logic | Charles A. Finnila | 1992-10-27 |