Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11887680 | Reducing program verifies for multi-level NAND cells | Jeffrey S. McNeil, Tommaso Vali | 2024-01-30 |
| 11823743 | Hybrid routine for a memory device | Shannon Hansen, Fulvio Rori, Andrea D'Alessandro, Chiara Cerafogli | 2023-11-21 |
| 11482298 | Device field degradation and factory defect detection by pump clock monitoring | Preston A. Thomson, Chi Ming Chu, Sheng-Huang Lee | 2022-10-25 |
| 11417406 | Reducing program verifies for multi-level NAND cells | Jeffrey S. McNeil, Tommaso Vali | 2022-08-16 |
| 11355200 | Hybrid routine for a memory device | Shannon Hansen, Fulvio Rori, Andrea D'Alessandro, Chiara Cerafogli | 2022-06-07 |
| 10665307 | Memory devices configured to perform leak checks | Jeffrey Kessenich, Joemar Sinipete, Chiming Chu, Kenneth W. Marr, Renato C. Padilla | 2020-05-26 |
| 10366767 | Memory devices configured to perform leak checks | Jeffrey Kessenich, Joemar Sinipete, Chiming Chu, Kenneth W. Marr, Renato C. Padilla | 2019-07-30 |
| 9761322 | Program operations with embedded leak checks | Jeffery A. Kessenich, Joemar Sinipete, Chiming Chu, Kenneth W. Marr, Renato C. Padilla | 2017-09-12 |
| 9281078 | Program operations with embedded leak checks | Jeffrey Kessenich, Joemar Sinipete, Chiming Chu, Kenneth W. Marr, Renato C. Padilla | 2016-03-08 |