Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8687434 | Circuits, devices, systems, and methods of operation for capturing data signals | — | 2014-04-01 |
| 8555127 | Self-timed error correcting code evaluation system and method | — | 2013-10-08 |
| 8533416 | Memory system and method using stacked memory device dice, and system using the memory system | Paul A. LaBerge, Joseph M. Jeddeloh | 2013-09-10 |
| 8521979 | Memory systems and methods for controlling the timing of receiving read data | Paul A. LaBerge | 2013-08-27 |
| 8468931 | Electro-mechanical control system for positioning fluid motors | — | 2013-06-25 |
| 8406071 | Strobe apparatus, systems, and methods | Paul A. LaBerge, Jake Klier | 2013-03-26 |
| 8347165 | Self-timed error correcting code evaluation system and method | — | 2013-01-01 |
| 8284617 | Circuits, devices, systems, and methods of operation for capturing data signals | — | 2012-10-09 |
| 8169841 | Strobe apparatus, systems, and methods | Paul A. LaBerge, Jake Klier | 2012-05-01 |
| 8154931 | Circuits, devices, systems, and methods of operation for capturing data signals | — | 2012-04-10 |
| 8040753 | System and method for capturing data signals using a data strobe signal | Joo S. Choi | 2011-10-18 |
| 8010866 | Memory system and method using stacked memory device dice, and system using the memory system | Paul A. LaBerge, Joseph M. Jeddeloh | 2011-08-30 |
| 7881149 | Write latency tracking using a delay lock loop in a synchronous DRAM | Feng Lin, Brent Keeth | 2011-02-01 |
| 7855931 | Memory system and method using stacked memory device dice, and system using the memory system | Paul A. LaBerge, Joseph M. Jeddeloh | 2010-12-21 |
| 7813192 | System and method for capturing data signals using a data strobe signal | Joo S. Choi | 2010-10-12 |
| 7787310 | Circuits, devices, systems, and methods of operation for capturing data signals | — | 2010-08-31 |
| 7660187 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | Brent Keeth, Feng Lin | 2010-02-09 |
| 7627793 | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems | — | 2009-12-01 |
| 7593286 | Write latency tracking using a delay lock loop in a synchronous DRAM | Feng Lin, Brent Keeth | 2009-09-22 |
| 7558133 | System and method for capturing data signals using a data strobe signal | Joo S. Choi | 2009-07-07 |
| 7480203 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | Brent Keeth, Feng Lin | 2009-01-20 |
| 7412634 | On-chip sampling circuit and method | Chris G. Martin, Troy A. Manning, Brent Keeth | 2008-08-12 |
| 7404124 | On-chip sampling circuit and method | Chris G. Martin, Troy A. Manning, Brent Keeth | 2008-07-22 |
| 7355920 | Write latency tracking using a delay lock loop in a synchronous DRAM | Feng Lin, Brent Keeth | 2008-04-08 |
| 7355922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | Brent Keeth, Feng Lin | 2008-04-08 |