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USPTO Patent Rankings Data through Dec 31, 2025
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Houfei Chen — 15 Patents

Micron: 13 patents #1,228 of 6,374Top 20%
Intel: 1 patents #18,326 of 30,777Top 60%
UWUniversity Of Washington: 1 patents #985 of 2,234Top 45%
Campbell, CA: #335 of 2,187 inventorsTop 20%
California: #40,789 of 386,348 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Houfei Chen has been granted 15 US patents while listed as an inventor at Micron. The first was granted in 2006 and the most recent in September 2025. Houfei Chen ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Houfei Chen in Campbell, CA, US.

Patents per Year

Patents granted per year, 2006 to 2025Bar chart with a peak of 3 patents in 2010.peak 32006: 1 patents20062008: 1 patents2009: 1 patents20092010: 3 patents2011: 2 patents20112012: 1 patents2013: 2 patents20132014: 1 patents2015: 1 patents20152017: 1 patents2025: 1 patents2025

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12416964 Methods and apparatus for bi-directional control of computing unit frequency Jianwei Dai, Jianfang Zhu, Ivan Chen, Deepak Samuel Kirubakaran, Rajshree Chabukswar +1 more 2025-09-16
9622358 Method for forming a circuit board via structure for high speed signaling Shiyou Zhao, Hao Wang 2017-04-11 $18,622,000
9055702 Method for forming a circuit board via structure for high speed signaling Shiyou Zhao, Hao Wang 2015-06-09 $11,836,000
8743555 Methods for suppressing power plane noise Shiyou Zhao 2014-06-03 $10,068,000
8516695 Method for forming a circuit board via structure for high speed signaling Shiyou Zhao, Hao Wang 2013-08-27 $4,465,000
8508950 Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise Shiyou Zhao 2013-08-13 $4,189,000
8243479 On-die anti-resonance structure for integrated circuit — 2012-08-14 $3,153,000
8023293 On-die anti-resonance structure for integrated circuit — 2011-09-20 $3,026,000
7992297 Method for forming a circuit board via structure for high speed signaling Shiyou Zhao, Hao Wang 2011-08-09 $2,316,000
7778039 Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise Shiyou Zhao 2010-08-17 $3,732,000
7676919 Method for forming a circuit board via structure for high speed signaling Shiyou Zhao, Hao Wang 2010-03-16 $5,174,000
7660708 S-matrix technique for circuit simulation — 2010-02-09 $4,497,000
7633773 On-die anti-resonance structure for integrated circuit — 2009-12-15 $5,540,000
7459638 Absorbing boundary for a multi-layer circuit board structure Shiyou Zhao, Hao Wang 2008-12-02 $734,000
7149666 Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures Leung W. Tsang, Chungchi Huang, Vikram Jandhyala 2006-12-12

Frequent Collaborators

Shiyou Zhao9 shared
Hao Wang6 shared
Deepak Samuel Kirubakaran1 shared
Jianwei Dai1 shared
Richard R. Winterton1 shared
Vikram Jandhyala1 shared

Nearby-Ranked Inventors

Naoya Kasahara15
Aaron Larry Snyder15
Avishay Meron15
Stuart Hatfield15
Satoshi KUNIYASU15
Ashton Mason15
Theodore Yuchiang Cheng15
Richard Sharbaugh15
Rajen Bhatt15