Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5951702 | RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU | Earl T. Cohen, Peter J. Vigil, Jengwei Pan, James S. Blomgren | 1999-09-14 |
| 5933024 | ECL to CMOS level translator using delayed feedback for high speed BICMOS applications | — | 1999-08-03 |
| 5920514 | Memory device with efficient redundancy using sense amplifiers | Brian P. Higgins | 1999-07-06 |
| RE36180 | Simultaneous read and refresh of different rows in a DRAM | — | 1999-04-06 |
| 5729156 | ECL to CMOS level translator using delayed feedback for high speed BiCMOS applications | — | 1998-03-17 |
| 5694368 | Memory device with efficient redundancy using sense amplifiers | Brian P. Higgins | 1997-12-02 |
| 5291443 | Simultaneous read and refresh of different rows in a dram | — | 1994-03-01 |
| 5122986 | Two transistor dram cell | — | 1992-06-16 |